130 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. APQ8084 TLMM block8 9maintainers:10 - Bjorn Andersson <bjorn.andersson@linaro.org>11 12description: |13 Top Level Mode Multiplexer pin controller in Qualcomm APQ8084 SoC.14 15allOf:16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#17 18properties:19 compatible:20 const: qcom,apq8084-pinctrl21 22 reg:23 maxItems: 124 25 interrupts:26 maxItems: 127 28 gpio-reserved-ranges: true29 30patternProperties:31 "-state$":32 oneOf:33 - $ref: "#/$defs/qcom-apq8084-tlmm-state"34 - patternProperties:35 "-pins$":36 $ref: "#/$defs/qcom-apq8084-tlmm-state"37 additionalProperties: false38 39$defs:40 qcom-apq8084-tlmm-state:41 type: object42 description:43 Pinctrl node's client devices use subnodes for desired pin configuration.44 Client device subnodes use below standard properties.45 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state46 unevaluatedProperties: false47 48 properties:49 pins:50 description:51 List of gpio pins affected by the properties specified in this52 subnode.53 items:54 oneOf:55 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-6])$"56 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,57 sdc2_data ]58 minItems: 159 maxItems: 3660 61 function:62 description:63 Specify the alternative function to be configured for the specified64 pins.65 enum: [ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,66 blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,67 blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,68 blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,69 blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,70 blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,71 blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,72 blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,73 blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,74 blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6,75 blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10,76 blsp_uart11, blsp_uart12, blsp_uim1, blsp_uim2,77 blsp_uim3, blsp_uim4, blsp_uim5, blsp_uim6, blsp_uim7,78 blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,79 blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,80 cci_async, cci_async_in0, cci_i2c0, cci_i2c1,81 cci_timer0, cci_timer1, cci_timer2, cci_timer3,82 cci_timer4, edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3,83 gcc_obt, gcc_vtt, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2,84 gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest,85 hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update,86 mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, pci_e1,87 pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,88 qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,89 sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,90 spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s,91 tsif1, tsif2, uim, uim_batt_alarm ]92 93 required:94 - pins95 96required:97 - compatible98 - reg99 100unevaluatedProperties: false101 102examples:103 - |104 #include <dt-bindings/interrupt-controller/arm-gic.h>105 tlmm: pinctrl@fd510000 {106 compatible = "qcom,apq8084-pinctrl";107 reg = <0xfd510000 0x4000>;108 109 gpio-controller;110 #gpio-cells = <2>;111 gpio-ranges = <&tlmm 0 0 147>;112 interrupt-controller;113 #interrupt-cells = <2>;114 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;115 116 uart-state {117 rx-pins {118 pins = "gpio5";119 function = "blsp_uart2";120 bias-pull-up;121 };122 123 tx-pins {124 pins = "gpio4";125 function = "blsp_uart2";126 bias-disable;127 };128 };129 };130