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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. MSM8909 TLMM block8 9maintainers:10 - Stephan Gerhold <stephan@gerhold.net>11 12description: |13 Top Level Mode Multiplexer pin controller in Qualcomm MSM8909 SoC.14 15allOf:16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#17 18properties:19 compatible:20 const: qcom,msm8909-tlmm21 22 reg:23 maxItems: 124 25 interrupts:26 maxItems: 127 28 gpio-reserved-ranges: true29 30patternProperties:31 "-state$":32 oneOf:33 - $ref: "#/$defs/qcom-msm8909-tlmm-state"34 - patternProperties:35 "-pins$":36 $ref: "#/$defs/qcom-msm8909-tlmm-state"37 additionalProperties: false38 39$defs:40 qcom-msm8909-tlmm-state:41 type: object42 description:43 Pinctrl node's client devices use subnodes for desired pin configuration.44 Client device subnodes use below standard properties.45 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state46 unevaluatedProperties: false47 48 properties:49 pins:50 description:51 List of gpio pins affected by the properties specified in this52 subnode.53 items:54 oneOf:55 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"56 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,57 sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,58 qdsd_data2, qdsd_data3 ]59 minItems: 160 maxItems: 1661 62 function:63 description:64 Specify the alternative function to be configured for the specified65 pins.66 enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,67 atest_char1, atest_char2, atest_char3, atest_combodac,68 atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1,69 bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3,70 blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1,71 blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1,72 blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1,73 blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,74 blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk,75 cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0,76 dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd,77 ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,78 gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio,79 gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync,80 nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2,81 pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a,82 pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b,83 pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b,84 prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,85 pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,86 pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,87 qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,88 qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,89 qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,90 qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s,91 smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present,92 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,93 uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt,94 wcss_bt, wcss_fm, wcss_wlan ]95 96 required:97 - pins98 99required:100 - compatible101 - reg102 103unevaluatedProperties: false104 105examples:106 - |107 #include <dt-bindings/interrupt-controller/arm-gic.h>108 109 pinctrl@1000000 {110 compatible = "qcom,msm8909-tlmm";111 reg = <0x1000000 0x300000>;112 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;113 gpio-controller;114 #gpio-cells = <2>;115 gpio-ranges = <&tlmm 0 0 113>;116 interrupt-controller;117 #interrupt-cells = <2>;118 119 gpio-wo-subnode-state {120 pins = "gpio1";121 function = "gpio";122 };123 124 uart-w-subnodes-state {125 rx-pins {126 pins = "gpio4";127 function = "blsp_uart1";128 bias-pull-up;129 };130 131 tx-pins {132 pins = "gpio5";133 function = "blsp_uart1";134 bias-disable;135 };136 };137 };138...139