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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SDM630 and SDM660 TLMM pin controller8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>12 13description:14 Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC.15 16allOf:17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#18 19properties:20 compatible:21 enum:22 - qcom,sdm630-pinctrl23 - qcom,sdm660-pinctrl24 25 reg:26 maxItems: 327 28 reg-names:29 items:30 - const: south31 - const: center32 - const: north33 34 interrupts:35 maxItems: 136 37 gpio-reserved-ranges:38 minItems: 139 maxItems: 5740 41 gpio-line-names:42 maxItems: 11443 44patternProperties:45 "-state$":46 oneOf:47 - $ref: "#/$defs/qcom-sdm630-tlmm-state"48 - patternProperties:49 "-pins$":50 $ref: "#/$defs/qcom-sdm630-tlmm-state"51 additionalProperties: false52 53$defs:54 qcom-sdm630-tlmm-state:55 type: object56 description:57 Pinctrl node's client devices use subnodes for desired pin configuration.58 Client device subnodes use below standard properties.59 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state60 unevaluatedProperties: false61 62 properties:63 pins:64 description:65 List of gpio pins affected by the properties specified in this66 subnode.67 items:68 oneOf:69 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"70 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,71 sdc2_cmd, sdc2_data ]72 minItems: 173 maxItems: 3674 75 function:76 description:77 Specify the alternative function to be configured for the specified78 pins.79 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,80 atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,81 atest_tsens, atest_tsens2, atest_usb1, atest_usb10,82 atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20,83 atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0,84 bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,85 blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b,86 blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,87 blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a,88 blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1,89 blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,90 blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c,91 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1,92 gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,93 isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,94 mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,95 nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,96 phase_flag1, phase_flag10, phase_flag11, phase_flag12,97 phase_flag13, phase_flag14, phase_flag15, phase_flag16,98 phase_flag17, phase_flag18, phase_flag19, phase_flag2,99 phase_flag20, phase_flag21, phase_flag22, phase_flag23,100 phase_flag24, phase_flag25, phase_flag26, phase_flag27,101 phase_flag28, phase_flag29, phase_flag3, phase_flag30,102 phase_flag31, phase_flag4, phase_flag5, phase_flag6,103 phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset,104 pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem,105 pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b,106 qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,107 qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2,108 qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,109 qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk,110 qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3,111 qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu,112 ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk,113 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,114 uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout,115 vsense_data0, vsense_data1, vsense_mode, wlan1_adc0,116 wlan1_adc1, wlan2_adc0, wlan2_adc1 ]117 118 required:119 - pins120 121required:122 - compatible123 - reg124 125unevaluatedProperties: false126 127examples:128 - |129 #include <dt-bindings/interrupt-controller/arm-gic.h>130 131 tlmm: pinctrl@3100000 {132 compatible = "qcom,sdm630-pinctrl";133 reg = <0x03100000 0x400000>,134 <0x03500000 0x400000>,135 <0x03900000 0x400000>;136 reg-names = "south", "center", "north";137 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;138 gpio-controller;139 gpio-ranges = <&tlmm 0 0 114>;140 #gpio-cells = <2>;141 interrupt-controller;142 #interrupt-cells = <2>;143 144 blsp1-uart1-default-state {145 pins = "gpio0", "gpio1", "gpio2", "gpio3";146 function = "gpio";147 drive-strength = <2>;148 bias-disable;149 };150 151 blsp2_uart1_default: blsp2-uart1-active-state {152 tx-rts-pins {153 pins = "gpio16", "gpio19";154 function = "blsp_uart5";155 drive-strength = <2>;156 bias-disable;157 };158 159 rx-pins {160 pins = "gpio17";161 function = "blsp_uart5";162 drive-strength = <2>;163 bias-pull-up;164 };165 166 cts-pins {167 pins = "gpio18";168 function = "blsp_uart5";169 drive-strength = <2>;170 bias-pull-down;171 };172 };173 };174