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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. SDM670 TLMM block8 9maintainers:10 - Richard Acayan <mailingradian@gmail.com>11 12description: |13 The Top Level Mode Multiplexer (TLMM) block found in the SDM670 platform.14 15allOf:16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#17 18properties:19 compatible:20 const: qcom,sdm670-tlmm21 22 reg:23 maxItems: 124 25 interrupts:26 maxItems: 127 28 gpio-reserved-ranges:29 minItems: 130 maxItems: 7531 32patternProperties:33 "-state$":34 oneOf:35 - $ref: "#/$defs/qcom-sdm670-tlmm-state"36 - patternProperties:37 "-pins$":38 $ref: "#/$defs/qcom-sdm670-tlmm-state"39 additionalProperties: false40 41$defs:42 qcom-sdm670-tlmm-state:43 type: object44 description:45 Pinctrl node's client devices use subnodes for desired pin configuration.46 Client device subnodes use below standard properties.47 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state48 unevaluatedProperties: false49 50 properties:51 pins:52 description:53 List of gpio pins affected by the properties specified in this54 subnode.55 items:56 oneOf:57 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"58 - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,59 sdc2_clk, sdc2_cmd, sdc2_data ]60 minItems: 161 maxItems: 3662 63 function:64 description:65 Specify the alternative function to be configured for the specified66 pins.67 68 enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10,69 atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,70 atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,71 cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist,72 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,73 gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update,74 lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,75 mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,76 pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,77 qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2,78 qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk,79 sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2,80 tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk,81 tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,82 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,83 vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ]84 85 required:86 - pins87 88required:89 - compatible90 - reg91 92unevaluatedProperties: false93 94examples:95 - |96 #include <dt-bindings/interrupt-controller/arm-gic.h>97 pinctrl@3400000 {98 compatible = "qcom,sdm670-tlmm";99 reg = <0x03400000 0x300000>;100 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;101 gpio-controller;102 #gpio-cells = <2>;103 interrupt-controller;104 #interrupt-cells = <2>;105 gpio-ranges = <&tlmm 0 0 151>;106 107 qup-i2c9-state {108 pins = "gpio6", "gpio7";109 function = "qup9";110 };111 };112...113