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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. SM4450 TLMM block8 9maintainers:10 - Tengfei Fan <quic_tengfan@quicinc.com>11 12description:13 Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC.14 15allOf:16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#17 18properties:19 compatible:20 const: qcom,sm4450-tlmm21 22 reg:23 maxItems: 124 25 interrupts: true26 interrupt-controller: true27 "#interrupt-cells": true28 gpio-controller: true29 30 gpio-reserved-ranges:31 minItems: 132 maxItems: 6833 34 gpio-line-names:35 maxItems: 13636 37 "#gpio-cells": true38 gpio-ranges: true39 wakeup-parent: true40 41patternProperties:42 "-state$":43 oneOf:44 - $ref: "#/$defs/qcom-sm4450-tlmm-state"45 - patternProperties:46 "-pins$":47 $ref: "#/$defs/qcom-sm4450-tlmm-state"48 additionalProperties: false49 50$defs:51 qcom-sm4450-tlmm-state:52 type: object53 description:54 Pinctrl node's client devices use subnodes for desired pin configuration.55 Client device subnodes use below standard properties.56 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state57 unevaluatedProperties: false58 59 properties:60 pins:61 description:62 List of gpio pins affected by the properties specified in this63 subnode.64 items:65 oneOf:66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$"67 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]68 minItems: 169 maxItems: 3670 71 function:72 description:73 Specify the alternative function to be configured for the specified74 pins.75 enum: [ gpio, atest_char, atest_usb0, audio_ref_clk, cam_mclk,76 cci_async_in0, cci_i2c, cci, cmu_rng, coex_uart1_rx,77 coex_uart1_tx, cri_trng, dbg_out_clk, ddr_bist,78 ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk, gcc_gp2_clk,79 gcc_gp3_clk, host2wlan_sol, ibi_i3c_qup0, ibi_i3c_qup1,80 jitter_bist_ref, mdp_vsync0_out, mdp_vsync1_out,81 mdp_vsync2_out, mdp_vsync3_out, mdp_vsync, nav,82 pcie0_clk_req, phase_flag, pll_bist_sync, pll_clk_aux,83 prng_rosc, qdss_cti_trig0, qdss_cti_trig1, qdss_gpio,84 qlink0_enable, qlink0_request, qlink0_wmss_reset,85 qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,86 qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2, qup1_se3,87 qup1_se4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2,88 tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,89 tgu_ch3_trigout, tmess_prng, tsense_pwm1_out,90 tsense_pwm2_out, uim0, uim1, usb0_hs_ac, usb0_phy_ps,91 vfr_0_mira, vfr_0_mirb, vfr_1, vsense_trigger_mirnat,92 wlan1_adc_dtest0, wlan1_adc_dtest1 ]93 94 required:95 - pins96 97required:98 - compatible99 - reg100 101additionalProperties: false102 103examples:104 - |105 #include <dt-bindings/interrupt-controller/arm-gic.h>106 tlmm: pinctrl@f100000 {107 compatible = "qcom,sm4450-tlmm";108 reg = <0x0f100000 0x300000>;109 gpio-controller;110 #gpio-cells = <2>;111 gpio-ranges = <&tlmm 0 0 137>;112 interrupt-controller;113 #interrupt-cells = <2>;114 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;115 116 gpio-wo-state {117 pins = "gpio1";118 function = "gpio";119 };120 121 uart-w-state {122 rx-pins {123 pins = "gpio23";124 function = "qup1_se2";125 bias-pull-up;126 };127 128 tx-pins {129 pins = "gpio22";130 function = "qup1_se2";131 bias-disable;132 };133 };134 };135...136