149 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. SM6350 TLMM block8 9maintainers:10 - Konrad Dybcio <konradybcio@kernel.org>11 12description:13 Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.14 15allOf:16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#17 18properties:19 compatible:20 const: qcom,sm6350-tlmm21 22 reg:23 maxItems: 124 25 interrupts:26 minItems: 927 maxItems: 928 29 gpio-reserved-ranges:30 minItems: 131 maxItems: 7832 33 gpio-line-names:34 maxItems: 15635 36patternProperties:37 "-state$":38 oneOf:39 - $ref: "#/$defs/qcom-sm6350-tlmm-state"40 - patternProperties:41 "-pins$":42 $ref: "#/$defs/qcom-sm6350-tlmm-state"43 additionalProperties: false44 45$defs:46 qcom-sm6350-tlmm-state:47 type: object48 description:49 Pinctrl node's client devices use subnodes for desired pin configuration.50 Client device subnodes use below standard properties.51 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state52 unevaluatedProperties: false53 54 properties:55 pins:56 description:57 List of gpio pins affected by the properties specified in this58 subnode.59 items:60 oneOf:61 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"62 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]63 minItems: 164 maxItems: 3665 66 function:67 description:68 Specify the alternative function to be configured for the specified69 pins.70 71 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2,72 atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11,73 atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22,74 atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,75 cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,76 cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3,77 dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,78 gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk,79 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2,80 mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1,81 phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,82 phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,83 phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,84 phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,85 phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9,86 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0,87 qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,88 qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,89 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss,90 qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11,91 qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data,92 rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write,93 sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,94 tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,95 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,96 wlan2_adc0, wlan2_adc1, ]97 98 required:99 - pins100 101required:102 - compatible103 - reg104 105unevaluatedProperties: false106 107examples:108 - |109 #include <dt-bindings/interrupt-controller/arm-gic.h>110 pinctrl@f100000 {111 compatible = "qcom,sm6350-tlmm";112 reg = <0x0f100000 0x300000>;113 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,114 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,115 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,116 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,117 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,118 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,119 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,120 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,121 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;122 123 gpio-controller;124 #gpio-cells = <2>;125 interrupt-controller;126 #interrupt-cells = <2>;127 gpio-ranges = <&tlmm 0 0 157>;128 129 gpio-wo-subnode-state {130 pins = "gpio1";131 function = "gpio";132 };133 134 uart-w-subnodes-state {135 rx-pins {136 pins = "gpio25";137 function = "qup13_f2";138 bias-disable;139 };140 141 tx-pins {142 pins = "gpio26";143 function = "qup13_f2";144 bias-disable;145 };146 };147 };148...149