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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. SM8350 TLMM block8 9maintainers:10 - Vinod Koul <vkoul@kernel.org>11 12description:13 Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC.14 15allOf:16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#17 18properties:19 compatible:20 const: qcom,sm8350-tlmm21 22 reg:23 maxItems: 124 25 interrupts:26 maxItems: 127 28 gpio-reserved-ranges:29 minItems: 130 maxItems: 10231 32 gpio-line-names:33 maxItems: 20334 35patternProperties:36 "-state$":37 oneOf:38 - $ref: "#/$defs/qcom-sm8350-tlmm-state"39 - patternProperties:40 "-pins$":41 $ref: "#/$defs/qcom-sm8350-tlmm-state"42 additionalProperties: false43 44$defs:45 qcom-sm8350-tlmm-state:46 type: object47 description:48 Pinctrl node's client devices use subnodes for desired pin configuration.49 Client device subnodes use below standard properties.50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state51 unevaluatedProperties: false52 53 properties:54 pins:55 description:56 List of gpio pins affected by the properties specified in this57 subnode.58 items:59 oneOf:60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$"61 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]62 minItems: 163 maxItems: 3664 65 function:66 description:67 Specify the alternative function to be configured for the specified68 pins.69 70 enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,71 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,72 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,73 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,74 gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,75 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,76 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,77 mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,78 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,79 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,80 mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,81 pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,82 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,83 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,84 qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,85 qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,86 qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,87 qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,88 qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,89 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,90 tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,91 uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,92 uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]93 94 required:95 - pins96 97required:98 - compatible99 - reg100 101unevaluatedProperties: false102 103examples:104 - |105 #include <dt-bindings/interrupt-controller/arm-gic.h>106 pinctrl@f100000 {107 compatible = "qcom,sm8350-tlmm";108 reg = <0x0f100000 0x300000>;109 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;110 gpio-controller;111 #gpio-cells = <2>;112 interrupt-controller;113 #interrupt-cells = <2>;114 gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */115 116 gpio-wo-subnode-state {117 pins = "gpio1";118 function = "gpio";119 };120 121 uart-w-subnodes-state {122 rx-pins {123 pins = "gpio18";124 function = "qup3";125 bias-pull-up;126 };127 128 tx-pins {129 pins = "gpio19";130 function = "qup3";131 bias-disable;132 };133 };134 };135...136