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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SM8550 SoC LPASS LPI TLMM8 9maintainers:10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>12 13description:14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.16 17properties:18 compatible:19 oneOf:20 - const: qcom,sm8550-lpass-lpi-pinctrl21 - items:22 - const: qcom,x1e80100-lpass-lpi-pinctrl23 - const: qcom,sm8550-lpass-lpi-pinctrl24 25 reg:26 items:27 - description: LPASS LPI TLMM Control and Status registers28 - description: LPASS LPI MCC registers29 30 clocks:31 items:32 - description: LPASS Core voting clock33 - description: LPASS Audio voting clock34 35 clock-names:36 items:37 - const: core38 - const: audio39 40patternProperties:41 "-state$":42 oneOf:43 - $ref: "#/$defs/qcom-sm8550-lpass-state"44 - patternProperties:45 "-pins$":46 $ref: "#/$defs/qcom-sm8550-lpass-state"47 additionalProperties: false48 49$defs:50 qcom-sm8550-lpass-state:51 type: object52 description:53 Pinctrl node's client devices use subnodes for desired pin configuration.54 Client device subnodes use below standard properties.55 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state56 unevaluatedProperties: false57 58 properties:59 pins:60 description:61 List of gpio pins affected by the properties specified in this62 subnode.63 items:64 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"65 66 function:67 enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,68 dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,69 ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,70 i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,71 i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,72 i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk,73 swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,74 wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]75 description:76 Specify the alternative function to be configured for the specified77 pins.78 79allOf:80 - $ref: qcom,lpass-lpi-common.yaml#81 82required:83 - compatible84 - reg85 - clocks86 - clock-names87 88unevaluatedProperties: false89 90examples:91 - |92 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>93 94 lpass_tlmm: pinctrl@6e80000 {95 compatible = "qcom,sm8550-lpass-lpi-pinctrl";96 reg = <0x06e80000 0x20000>,97 <0x0725a000 0x10000>;98 99 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,100 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;101 clock-names = "core", "audio";102 103 gpio-controller;104 #gpio-cells = <2>;105 gpio-ranges = <&lpass_tlmm 0 0 23>;106 107 tx-swr-sleep-clk-state {108 pins = "gpio0";109 function = "swr_tx_clk";110 drive-strength = <2>;111 bias-pull-down;112 };113 };114