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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SM8650 SoC LPASS LPI TLMM8 9maintainers:10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>12 13description:14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem15 (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC.16 17properties:18 compatible:19 const: qcom,sm8650-lpass-lpi-pinctrl20 21 reg:22 items:23 - description: LPASS LPI TLMM Control and Status registers24 25 clocks:26 items:27 - description: LPASS Core voting clock28 - description: LPASS Audio voting clock29 30 clock-names:31 items:32 - const: core33 - const: audio34 35patternProperties:36 "-state$":37 oneOf:38 - $ref: "#/$defs/qcom-sm8650-lpass-state"39 - patternProperties:40 "-pins$":41 $ref: "#/$defs/qcom-sm8650-lpass-state"42 additionalProperties: false43 44$defs:45 qcom-sm8650-lpass-state:46 type: object47 description:48 Pinctrl node's client devices use subnodes for desired pin configuration.49 Client device subnodes use below standard properties.50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state51 unevaluatedProperties: false52 53 properties:54 pins:55 description:56 List of gpio pins affected by the properties specified in this57 subnode.58 items:59 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"60 61 function:62 enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,63 dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,64 ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,65 i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,66 i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,67 i2s4_data, i2s4_ws, qca_swr_clk, qca_swr_data, slimbus_clk,68 slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data,69 wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]70 description:71 Specify the alternative function to be configured for the specified72 pins.73 74allOf:75 - $ref: qcom,lpass-lpi-common.yaml#76 77required:78 - compatible79 - reg80 - clocks81 - clock-names82 83unevaluatedProperties: false84 85examples:86 - |87 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>88 89 lpass_tlmm: pinctrl@6e80000 {90 compatible = "qcom,sm8650-lpass-lpi-pinctrl";91 reg = <0x06e80000 0x20000>;92 93 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,94 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;95 clock-names = "core", "audio";96 97 gpio-controller;98 #gpio-cells = <2>;99 gpio-ranges = <&lpass_tlmm 0 0 23>;100 101 tx-swr-sleep-clk-state {102 pins = "gpio0";103 function = "swr_tx_clk";104 drive-strength = <2>;105 bias-pull-down;106 };107 };108