188 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright 2023 Realtek Semiconductor Corporation3%YAML 1.24---5$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1319d-pinctrl.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Realtek DHC RTD1319D Pin Controller9 10maintainers:11 - TY Chang <tychang@realtek.com>12 13description:14 The Realtek DHC RTD1319D is a high-definition media processor SoC. The15 RTD1319D pin controller is used to control pin function, pull up/down16 resistor, drive strength, schmitt trigger and power source.17 18properties:19 compatible:20 const: realtek,rtd1319d-pinctrl21 22 reg:23 maxItems: 124 25patternProperties:26 '-pins$':27 type: object28 allOf:29 - $ref: pincfg-node.yaml#30 - $ref: pinmux-node.yaml#31 32 properties:33 pins:34 items:35 enum: [ gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7,36 gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, gpio_14,37 gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, gpio_21,38 gpio_22, gpio_23, usb_cc2, gpio_25, gpio_26, gpio_27, gpio_28,39 gpio_29, gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35,40 hif_data, hif_en, hif_rdy, hif_clk, gpio_40, gpio_41, gpio_42,41 gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, gpio_48, gpio_49,42 gpio_50, usb_cc1, gpio_52, gpio_53, ir_rx, ur0_rx, ur0_tx,43 gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_63,44 gpio_64, emmc_rst_n, emmc_dd_sb, emmc_clk, emmc_cmd, emmc_data_0,45 emmc_data_1, emmc_data_2, emmc_data_3, emmc_data_4, emmc_data_5,46 emmc_data_6, emmc_data_7, dummy, gpio_78, gpio_79, gpio_80,47 gpio_81, ur2_loc, gspi_loc, hi_width, sf_en, arm_trace_dbg_en,48 ejtag_aucpu_loc, ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc,49 dmic_loc, ejtag_secpu_loc, vtc_dmic_loc, vtc_tdm_loc, vtc_i2si_loc,50 tdm_ai_loc, ai_loc, spdif_loc, hif_en_loc, sc0_loc, sc1_loc,51 scan_switch, wd_rset, boot_sel, reset_n, testmode ]52 53 function:54 enum: [ gpio, nf, emmc, tp0, tp1, sc0, sc0_data0, sc0_data1, sc0_data2,55 sc1, sc1_data0, sc1_data1, sc1_data2, ao, gspi_loc0, gspi_loc1,56 uart0, uart1, uart2_loc0, uart2_loc1, i2c0, i2c1, i2c3, i2c4,57 i2c5, pcie1, sdio, etn_led, etn_phy, spi, pwm0_loc0, pwm0_loc1,58 pwm1_loc0, pwm1_loc1, pwm2_loc0, pwm2_loc1, pwm3_loc0, pwm3_loc1,59 qam_agc_if0, qam_agc_if1, spdif_optical_loc0, spdif_optical_loc1,60 usb_cc1, usb_cc2, vfd, sd, dmic_loc0, dmic_loc1, ai_loc0, ai_loc1,61 tdm_ai_loc0, tdm_ai_loc1, hi_loc0, hi_m, vtc_i2so, vtc_i2si_loc0,62 vtc_i2si_loc1, vtc_dmic_loc0, vtc_dmic_loc1, vtc_tdm_loc0,63 vtc_tdm_loc1, dc_fan, pll_test_loc0, pll_test_loc1, ir_rx,64 uart2_disable, gspi_disable, hi_width_disable, hi_width_1bit,65 sf_disable, sf_enable, scpu_ejtag_loc0, scpu_ejtag_loc1,66 scpu_ejtag_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2,67 vcpu_ejtag_loc0, vcpu_ejtag_loc1, vcpu_ejtag_loc2, secpu_ejtag_loc0,68 secpu_ejtag_loc1, secpu_ejtag_loc2, aucpu_ejtag_loc0, aucpu_ejtag_loc1,69 aucpu_ejtag_loc2, iso_tristate, dbg_out0, dbg_out1, standby_dbg,70 spdif, arm_trace_debug_disable, arm_trace_debug_enable,71 aucpu_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable,72 scpu_ejtag_disable, secpu_ejtag_disable, vtc_dmic_loc_disable,73 vtc_tdm_disable, vtc_i2si_disable, tdm_ai_disable, ai_disable,74 spdif_disable, hif_disable, hif_enable, test_loop, pmic_pwrup ]75 76 drive-strength:77 enum: [4, 8]78 79 bias-pull-down: true80 81 bias-pull-up: true82 83 bias-disable: true84 85 input-schmitt-enable: true86 87 input-schmitt-disable: true88 89 drive-push-pull: true90 91 power-source:92 description: |93 Valid arguments are described as below:94 0: power supply of 1.8V95 1: power supply of 3.3V96 enum: [0, 1]97 98 realtek,drive-strength-p:99 description: |100 Some of pins can be driven using the P-MOS and N-MOS transistor to101 achieve finer adjustments. The block-diagram representation is as102 follows:103 VDD104 |105 ||--+106 +-----o|| P-MOS-FET107 | ||--+108 IN --+ +----- out109 | ||--+110 +------|| N-MOS-FET111 ||--+112 |113 GND114 The driving strength of the P-MOS/N-MOS transistors impacts the115 waveform's rise/fall times. Greater driving strength results in116 shorter rise/fall times. Each P-MOS and N-MOS transistor offers117 8 configurable levels (0 to 7), with higher values indicating118 greater driving strength, contributing to achieving the desired119 speed.120 121 The realtek,drive-strength-p is used to control the driving strength122 of the P-MOS output.123 $ref: /schemas/types.yaml#/definitions/uint32124 minimum: 0125 maximum: 7126 127 realtek,drive-strength-n:128 description: |129 Similar to the realtek,drive-strength-p, the realtek,drive-strength-n130 is used to control the driving strength of the N-MOS output.131 $ref: /schemas/types.yaml#/definitions/uint32132 minimum: 0133 maximum: 7134 135 realtek,duty-cycle:136 description: |137 An integer describing the level to adjust output duty cycle, controlling138 the proportion of positive and negative waveforms in nanoseconds.139 Valid arguments are described as below:140 0: 0ns141 2: + 0.25ns142 3: + 0.5ns143 4: -0.25ns144 5: -0.5ns145 $ref: /schemas/types.yaml#/definitions/uint32146 enum: [ 0, 2, 3, 4, 5 ]147 148 required:149 - pins150 151 additionalProperties: false152 153required:154 - compatible155 - reg156 157additionalProperties: false158 159examples:160 - |161 pinctrl@4e000 {162 compatible = "realtek,rtd1319d-pinctrl";163 reg = <0x4e000 0x130>;164 165 emmc-hs200-pins {166 pins = "emmc_clk",167 "emmc_cmd",168 "emmc_data_0",169 "emmc_data_1",170 "emmc_data_2",171 "emmc_data_3",172 "emmc_data_4",173 "emmc_data_5",174 "emmc_data_6",175 "emmc_data_7";176 function = "emmc";177 realtek,drive-strength-p = <0x2>;178 realtek,drive-strength-n = <0x2>;179 };180 181 i2c-0-pins {182 pins = "gpio_12",183 "gpio_13";184 function = "i2c0";185 drive-strength = <4>;186 };187 };188