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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/G2L Port Output Enable for GPT (POEG)8 9maintainers:10  - Biju Das <biju.das.jz@bp.renesas.com>11 12description: |13  The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be14  disabled by using the port output enabling function for the GPT (POEG).15  Specifically, either of the following ways can be used.16  * Input level detection of the GTETRGA to GTETRGD pins.17  * Output-disable request from the GPT.18  * SSF bit setting(ie, by setting POEGGn.SSF to 1)19 20  The state of the GTIOCxA and the GTIOCxB pins when the output is disabled,21  are controlled by the GPT module.22 23properties:24  compatible:25    items:26      - enum:27          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}28          - renesas,r9a07g054-poeg  # RZ/V2L29      - const: renesas,rzg2l-poeg30 31  reg:32    maxItems: 133 34  interrupts:35    maxItems: 136 37  clocks:38    maxItems: 139 40  power-domains:41    maxItems: 142 43  resets:44    maxItems: 145 46  renesas,gpt:47    $ref: /schemas/types.yaml#/definitions/phandle48    description: phandle to gpt instance that serves the pwm operation.49 50  renesas,poeg-id:51    $ref: /schemas/types.yaml#/definitions/uint3252    enum: [ 0, 1, 2, 3 ]53    description: |54      POEG group index. Valid values are:55        <0> : POEG group A56        <1> : POEG group B57        <2> : POEG group C58        <3> : POEG group D59 60required:61  - compatible62  - reg63  - interrupts64  - clocks65  - power-domains66  - resets67  - renesas,poeg-id68  - renesas,gpt69 70additionalProperties: false71 72examples:73  - |74    #include <dt-bindings/clock/r9a07g044-cpg.h>75    #include <dt-bindings/interrupt-controller/arm-gic.h>76 77    poeggd: poeg@10049400 {78        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";79        reg = <0x10049400 0x400>;80        interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;81        clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;82        power-domains = <&cpg>;83        resets = <&cpg R9A07G044_POEG_D_RST>;84        renesas,poeg-id = <3>;85        renesas,gpt = <&gpt>;86    };87