129 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/N1 Pin Controller8 9maintainers:10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>11 - Geert Uytterhoeven <geert+renesas@glider.be>12 13properties:14 compatible:15 items:16 - enum:17 - renesas,r9a06g032-pinctrl # RZ/N1D18 - renesas,r9a06g033-pinctrl # RZ/N1S19 - const: renesas,rzn1-pinctrl # Generic RZ/N120 21 reg:22 items:23 - description: GPIO Multiplexing Level1 Register Block24 - description: GPIO Multiplexing Level2 Register Block25 26 clocks:27 maxItems: 128 29 clock-names:30 const: bus31 description:32 The bus clock, sometimes described as pclk, for register accesses.33 34allOf:35 - $ref: pinctrl.yaml#36 37required:38 - compatible39 - reg40 - clocks41 - clock-names42 43additionalProperties:44 anyOf:45 - type: object46 allOf:47 - $ref: pincfg-node.yaml#48 - $ref: pinmux-node.yaml#49 50 description:51 A pin multiplexing sub-node describes how to configure a set of (or a52 single) pin in some desired alternate function mode.53 A single sub-node may define several pin configurations.54 55 properties:56 pinmux:57 description: |58 Integer array representing pin number and pin multiplexing59 configuration.60 When a pin has to be configured in alternate function mode, use61 this property to identify the pin by its global index, and provide62 its alternate function configuration number along with it.63 When multiple pins are required to be configured as part of the64 same alternate function they shall be specified as members of the65 same argument list of a single "pinmux" property.66 Integers values in the "pinmux" argument list are assembled as:67 (PIN | MUX_FUNC << 8)68 where PIN directly corresponds to the pl_gpio pin number and69 MUX_FUNC is one of the alternate function identifiers defined in:70 <include/dt-bindings/pinctrl/rzn1-pinctrl.h>71 These identifiers collapse the IO Multiplex Configuration Level 172 and Level 2 numbers that are detailed in the hardware reference73 manual into a single number. The identifiers for Level 2 are simply74 offset by 10. Additional identifiers are provided to specify the75 MDIO source peripheral.76 77 bias-disable: true78 bias-pull-up:79 description: Pull up the pin with 50 kOhm80 bias-pull-down:81 description: Pull down the pin with 50 kOhm82 bias-high-impedance: true83 drive-strength:84 enum: [ 4, 6, 8, 12 ]85 86 required:87 - pinmux88 89 additionalProperties:90 $ref: "#/additionalProperties/anyOf/0"91 92 - type: object93 additionalProperties:94 $ref: "#/additionalProperties/anyOf/0"95 96examples:97 - |98 #include <dt-bindings/clock/r9a06g032-sysctrl.h>99 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>100 pinctrl: pinctrl@40067000 {101 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";102 reg = <0x40067000 0x1000>, <0x51000000 0x480>;103 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;104 clock-names = "bus";105 106 /*107 * A serial communication interface with a TX output pin and an RX108 * input pin.109 */110 pins_uart0: pins_uart0 {111 pinmux = <112 RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */113 RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */114 >;115 };116 117 /*118 * Set the pull-up on the RXD pin of the UART.119 */120 pins_uart0_alt: pins_uart0_alt {121 pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;122 123 pins_uart6_rx {124 pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;125 bias-pull-up;126 };127 };128 };129