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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Mediatek Power Domains Controller8 9maintainers:10 - MandyJH Liu <mandyjh.liu@mediatek.com>11 - Matthias Brugger <mbrugger@suse.com>12 13description: |14 Mediatek processors include support for multiple power domains which can be15 powered up/down by software based on different application scenes to save power.16 17 IP cores belonging to a power domain should contain a 'power-domains'18 property that is a phandle for SCPSYS node representing the domain.19 20properties:21 $nodename:22 pattern: '^power-controller(@[0-9a-f]+)?$'23 24 compatible:25 enum:26 - mediatek,mt6795-power-controller27 - mediatek,mt8167-power-controller28 - mediatek,mt8173-power-controller29 - mediatek,mt8183-power-controller30 - mediatek,mt8186-power-controller31 - mediatek,mt8188-power-controller32 - mediatek,mt8192-power-controller33 - mediatek,mt8195-power-controller34 - mediatek,mt8365-power-controller35 36 '#power-domain-cells':37 const: 138 39 '#address-cells':40 const: 141 42 '#size-cells':43 const: 044 45patternProperties:46 "^power-domain@[0-9a-f]+$":47 $ref: "#/$defs/power-domain-node"48 patternProperties:49 "^power-domain@[0-9a-f]+$":50 $ref: "#/$defs/power-domain-node"51 patternProperties:52 "^power-domain@[0-9a-f]+$":53 $ref: "#/$defs/power-domain-node"54 patternProperties:55 "^power-domain@[0-9a-f]+$":56 $ref: "#/$defs/power-domain-node"57 unevaluatedProperties: false58 unevaluatedProperties: false59 unevaluatedProperties: false60 unevaluatedProperties: false61 62$defs:63 power-domain-node:64 type: object65 description: |66 Represents the power domains within the power controller node as documented67 in Documentation/devicetree/bindings/power/power-domain.yaml.68 69 properties:70 71 '#power-domain-cells':72 description:73 Must be 0 for nodes representing a single PM domain and 1 for nodes74 providing multiple PM domains.75 76 '#address-cells':77 const: 178 79 '#size-cells':80 const: 081 82 reg:83 description: |84 Power domain index. Valid values are defined in:85 "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.86 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.87 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.88 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.89 "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.90 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.91 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.92 "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.93 maxItems: 194 95 clocks:96 description: |97 A number of phandles to clocks that need to be enabled during domain98 power-up sequencing.99 100 clock-names:101 description: |102 List of names of clocks, in order to match the power-up sequencing103 for each power domain we need to group the clocks by name. BASIC104 clocks need to be enabled before enabling the corresponding power105 domain, and should not have a '-' in their name (i.e mm, mfg, venc).106 SUSBYS clocks need to be enabled before releasing the bus protection,107 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).108 109 In order to follow properly the power-up sequencing, the clocks must110 be specified by order, adding first the BASIC clocks followed by the111 SUSBSYS clocks.112 113 domain-supply:114 description: domain regulator supply.115 116 mediatek,infracfg:117 $ref: /schemas/types.yaml#/definitions/phandle118 description: phandle to the device containing the INFRACFG register range.119 120 mediatek,infracfg-nao:121 $ref: /schemas/types.yaml#/definitions/phandle122 description: phandle to the device containing the INFRACFG-NAO register range.123 124 mediatek,smi:125 $ref: /schemas/types.yaml#/definitions/phandle126 description: phandle to the device containing the SMI register range.127 128 required:129 - reg130 131required:132 - compatible133 134additionalProperties: false135 136examples:137 - |138 #include <dt-bindings/clock/mt8173-clk.h>139 #include <dt-bindings/power/mt8173-power.h>140 141 soc {142 #address-cells = <2>;143 #size-cells = <2>;144 145 scpsys: syscon@10006000 {146 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";147 reg = <0 0x10006000 0 0x1000>;148 149 spm: power-controller {150 compatible = "mediatek,mt8173-power-controller";151 #address-cells = <1>;152 #size-cells = <0>;153 #power-domain-cells = <1>;154 155 /* power domains of the SoC */156 power-domain@MT8173_POWER_DOMAIN_VDEC {157 reg = <MT8173_POWER_DOMAIN_VDEC>;158 clocks = <&topckgen CLK_TOP_MM_SEL>;159 clock-names = "mm";160 #power-domain-cells = <0>;161 };162 power-domain@MT8173_POWER_DOMAIN_VENC {163 reg = <MT8173_POWER_DOMAIN_VENC>;164 clocks = <&topckgen CLK_TOP_MM_SEL>,165 <&topckgen CLK_TOP_VENC_SEL>;166 clock-names = "mm", "venc";167 #power-domain-cells = <0>;168 };169 power-domain@MT8173_POWER_DOMAIN_ISP {170 reg = <MT8173_POWER_DOMAIN_ISP>;171 clocks = <&topckgen CLK_TOP_MM_SEL>;172 clock-names = "mm";173 #power-domain-cells = <0>;174 };175 power-domain@MT8173_POWER_DOMAIN_MM {176 reg = <MT8173_POWER_DOMAIN_MM>;177 clocks = <&topckgen CLK_TOP_MM_SEL>;178 clock-names = "mm";179 #power-domain-cells = <0>;180 mediatek,infracfg = <&infracfg>;181 };182 power-domain@MT8173_POWER_DOMAIN_VENC_LT {183 reg = <MT8173_POWER_DOMAIN_VENC_LT>;184 clocks = <&topckgen CLK_TOP_MM_SEL>,185 <&topckgen CLK_TOP_VENC_LT_SEL>;186 clock-names = "mm", "venclt";187 #power-domain-cells = <0>;188 };189 power-domain@MT8173_POWER_DOMAIN_AUDIO {190 reg = <MT8173_POWER_DOMAIN_AUDIO>;191 #power-domain-cells = <0>;192 };193 power-domain@MT8173_POWER_DOMAIN_USB {194 reg = <MT8173_POWER_DOMAIN_USB>;195 #power-domain-cells = <0>;196 };197 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {198 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;199 clocks = <&clk26m>;200 clock-names = "mfg";201 #address-cells = <1>;202 #size-cells = <0>;203 #power-domain-cells = <1>;204 205 power-domain@MT8173_POWER_DOMAIN_MFG_2D {206 reg = <MT8173_POWER_DOMAIN_MFG_2D>;207 #address-cells = <1>;208 #size-cells = <0>;209 #power-domain-cells = <1>;210 211 power-domain@MT8173_POWER_DOMAIN_MFG {212 reg = <MT8173_POWER_DOMAIN_MFG>;213 #power-domain-cells = <0>;214 mediatek,infracfg = <&infracfg>;215 };216 };217 };218 };219 };220 };221