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1===================================================================2Power Architecture CPU Binding3Copyright 2013 Freescale Semiconductor Inc.4 5Power Architecture CPUs in Freescale SOCs are represented in device trees as6per the definition in the Devicetree Specification.7 8In addition to the Devicetree Specification definitions, the properties9defined below may be present on CPU nodes.10 11PROPERTIES12 13 - fsl,eref-*14 Usage: optional15 Value type: <empty>16 Definition: The EREF (EREF: A Programmer.s Reference Manual for17 Freescale Power Architecture) defines the architecture for Freescale18 Power CPUs. The EREF defines some architecture categories not defined19 by the Power ISA. For these EREF-specific categories, the existence of20 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category21 name with all uppercase letters converted to lowercase, indicates that22 the category is supported by the implementation.23 24 - fsl,portid-mapping25 Usage: optional26 Value type: <u32>27 Definition: The Coherency Subdomain ID Port Mapping Registers and28 Snoop ID Port Mapping registers, which are part of the CoreNet29 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain30 ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from31 these registers should be set if the corresponding CPU should be32 snooped. This property defines a bitmask which selects the bit33 that should be set if this cpu should be snooped.34