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1===================================================================2Debug Control and Status Register (DCSR) Binding3Copyright 2011 Freescale Semiconductor Inc.4 5NOTE: The bindings described in this document are preliminary and subject6to change. Some of the compatible strings that contain only generic names7may turn out to be inappropriate, or need additional properties to describe8the integration of the block with the rest of the chip.9 10=====================================================================11Debug Control and Status Register Memory Map12 13Description14 15This node defines the base address and range for the16defined DCSR Memory Map. Child nodes will describe the individual17debug blocks defined within this memory space.18 19PROPERTIES20 21 - compatible22 Usage: required23 Value type: <string>24 Definition: Must include "fsl,dcsr" and "simple-bus".25 The DCSR space exists in the memory-mapped bus.26 27 - #address-cells28 Usage: required29 Value type: <u32>30 Definition: A standard property. Defines the number of cells31 or representing physical addresses in child nodes.32 33 - #size-cells34 Usage: required35 Value type: <u32>36 Definition: A standard property. Defines the number of cells37 or representing the size of physical addresses in38 child nodes.39 40 - ranges41 Usage: required42 Value type: <prop-encoded-array>43 Definition: A standard property. Specifies the physical address44 range of the DCSR space.45 46EXAMPLE47 dcsr: dcsr@f00000000 {48 #address-cells = <1>;49 #size-cells = <1>;50 compatible = "fsl,dcsr", "simple-bus";51 ranges = <0x00000000 0xf 0x00000000 0x01008000>;52 };53 54=====================================================================55Event Processing Unit56 57This node represents the region of DCSR space allocated to the EPU58 59PROPERTIES60 61 - compatible62 Usage: required63 Value type: <string>64 Definition: Must include "fsl,dcsr-epu"65 66 - interrupts67 Usage: required68 Value type: <prop_encoded-array>69 Definition: Specifies the interrupts generated by the EPU.70 The value of the interrupts property consists of three71 interrupt specifiers. The format of the specifier is defined72 by the binding document describing the node's interrupt parent.73 74 The EPU counters can be configured to assert the performance75 monitor interrupt signal based on either counter overflow or value76 match. Which counter asserted the interrupt is captured in an EPU77 Counter Interrupt Status Register (EPCPUISR).78 79 The EPU unit can also be configured to assert either or both of80 two interrupt signals based on debug event sources within the SoC.81 The interrupt signals are epu_xt_int0 and epu_xt_int1.82 Which event source asserted the interrupt is captured in an EPU83 Interrupt Status Register (EPISR0,EPISR1).84 85 Interrupt numbers are listed in order (perfmon, event0, event1).86 87 - reg88 Usage: required89 Value type: <prop-encoded-array>90 Definition: A standard property. Specifies the physical address91 offset and length of the DCSR space registers of the device92 configuration block.93 94EXAMPLE95 dcsr-epu@0 {96 compatible = "fsl,dcsr-epu";97 interrupts = <52 2 0 098 84 2 0 099 85 2 0 0>;100 interrupt-parent = <&mpic>;101 reg = <0x0 0x1000>;102 };103 104=======================================================================105Nexus Port Controller106 107This node represents the region of DCSR space allocated to the NPC108 109PROPERTIES110 111 - compatible112 Usage: required113 Value type: <string>114 Definition: Must include "fsl,dcsr-npc"115 116 - reg117 Usage: required118 Value type: <prop-encoded-array>119 Definition: A standard property. Specifies the physical address120 offset and length of the DCSR space registers of the device121 configuration block.122 The Nexus Port controller occupies two regions in the DCSR space123 with distinct functionality.124 125 The first register range describes the Nexus Port Controller126 control and status registers.127 128 The second register range describes the Nexus Port Controller129 internal trace buffer. The NPC trace buffer is a small memory buffer130 which stages the nexus trace data for transmission via the Aurora port131 or to a DDR based trace buffer. In some configurations the NPC trace132 buffer can be the only trace buffer used.133 134 135EXAMPLE136 dcsr-npc {137 compatible = "fsl,dcsr-npc";138 reg = <0x1000 0x1000 0x1000000 0x8000>;139 };140 141=======================================================================142Nexus Concentrator143 144This node represents the region of DCSR space allocated to the NXC145 146PROPERTIES147 148 - compatible149 Usage: required150 Value type: <string>151 Definition: Must include "fsl,dcsr-nxc"152 153 - reg154 Usage: required155 Value type: <prop-encoded-array>156 Definition: A standard property. Specifies the physical address157 offset and length of the DCSR space registers of the device158 configuration block.159 160EXAMPLE161 dcsr-nxc@2000 {162 compatible = "fsl,dcsr-nxc";163 reg = <0x2000 0x1000>;164 };165=======================================================================166CoreNet Debug Controller167 168This node represents the region of DCSR space allocated to169the CoreNet Debug controller.170 171PROPERTIES172 173 - compatible174 Usage: required175 Value type: <string>176 Definition: Must include "fsl,dcsr-corenet"177 178 - reg179 Usage: required180 Value type: <prop-encoded-array>181 Definition: A standard property. Specifies the physical address182 offset and length of the DCSR space registers of the device183 configuration block.184 The CoreNet Debug controller occupies two regions in the DCSR space185 with distinct functionality.186 187 The first register range describes the CoreNet Debug Controller188 functionality to perform transaction and transaction attribute matches.189 190 The second register range describes the CoreNet Debug Controller191 functionality to trigger event notifications and debug traces.192 193EXAMPLE194 dcsr-corenet {195 compatible = "fsl,dcsr-corenet";196 reg = <0x8000 0x1000 0xB0000 0x1000>;197 };198 199=======================================================================200Data Path Debug controller201 202This node represents the region of DCSR space allocated to203the DPAA Debug Controller. This controller controls debug configuration204for the QMAN and FMAN blocks.205 206PROPERTIES207 208 - compatible209 Usage: required210 Value type: <string>211 Definition: Must include both an identifier specific to the SoC212 or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the213 generic compatible string "fsl,dcsr-dpaa".214 215 - reg216 Usage: required217 Value type: <prop-encoded-array>218 Definition: A standard property. Specifies the physical address219 offset and length of the DCSR space registers of the device220 configuration block.221 222EXAMPLE223 dcsr-dpaa@9000 {224 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";225 reg = <0x9000 0x1000>;226 };227 228=======================================================================229OCeaN Debug controller230 231This node represents the region of DCSR space allocated to232the OCN Debug Controller.233 234PROPERTIES235 236 - compatible237 Usage: required238 Value type: <string>239 Definition: Must include both an identifier specific to the SoC240 or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the241 generic compatible string "fsl,dcsr-ocn".242 243 - reg244 Usage: required245 Value type: <prop-encoded-array>246 Definition: A standard property. Specifies the physical address247 offset and length of the DCSR space registers of the device248 configuration block.249 250EXAMPLE251 dcsr-ocn@11000 {252 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";253 reg = <0x11000 0x1000>;254 };255 256=======================================================================257DDR Controller Debug controller258 259This node represents the region of DCSR space allocated to260the OCN Debug Controller.261 262PROPERTIES263 264 - compatible265 Usage: required266 Value type: <string>267 Definition: Must include "fsl,dcsr-ddr"268 269 - dev-handle270 Usage: required271 Definition: A phandle to associate this debug node with its272 component controller.273 274 - reg275 Usage: required276 Value type: <prop-encoded-array>277 Definition: A standard property. Specifies the physical address278 offset and length of the DCSR space registers of the device279 configuration block.280 281EXAMPLE282 dcsr-ddr@12000 {283 compatible = "fsl,dcsr-ddr";284 dev-handle = <&ddr1>;285 reg = <0x12000 0x1000>;286 };287 288=======================================================================289Nexus Aurora Link Controller290 291This node represents the region of DCSR space allocated to292the NAL Controller.293 294PROPERTIES295 296 - compatible297 Usage: required298 Value type: <string>299 Definition: Must include both an identifier specific to the SoC300 or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the301 generic compatible string "fsl,dcsr-nal".302 303 - reg304 Usage: required305 Value type: <prop-encoded-array>306 Definition: A standard property. Specifies the physical address307 offset and length of the DCSR space registers of the device308 configuration block.309 310EXAMPLE311 dcsr-nal@18000 {312 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";313 reg = <0x18000 0x1000>;314 };315 316 317=======================================================================318Run Control and Power Management319 320This node represents the region of DCSR space allocated to321the RCPM Debug Controller. This functionlity is limited to the322control the debug operations of the SoC and cores.323 324PROPERTIES325 326 - compatible327 Usage: required328 Value type: <string>329 Definition: Must include both an identifier specific to the SoC330 or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the331 generic compatible string "fsl,dcsr-rcpm".332 333 - reg334 Usage: required335 Value type: <prop-encoded-array>336 Definition: A standard property. Specifies the physical address337 offset and length of the DCSR space registers of the device338 configuration block.339 340EXAMPLE341 dcsr-rcpm@22000 {342 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";343 reg = <0x22000 0x1000>;344 };345 346=======================================================================347Core Service Bridge Proxy348 349This node represents the region of DCSR space allocated to350the Core Service Bridge Proxies.351There is one Core Service Bridge Proxy device for each CPU in the system.352This functionlity provides access to the debug operations of the CPU.353 354PROPERTIES355 356 - compatible357 Usage: required358 Value type: <string>359 Definition: Must include both an identifier specific to the cpu360 of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the361 generic compatible string "fsl,dcsr-cpu-sb-proxy".362 363 - cpu-handle364 Usage: required365 Definition: A phandle to associate this debug node with its cpu.366 367 - reg368 Usage: required369 Value type: <prop-encoded-array>370 Definition: A standard property. Specifies the physical address371 offset and length of the DCSR space registers of the device372 configuration block.373 374EXAMPLE375 dcsr-cpu-sb-proxy@40000 {376 compatible = "fsl,dcsr-e500mc-sb-proxy",377 "fsl,dcsr-cpu-sb-proxy";378 cpu-handle = <&cpu0>;379 reg = <0x40000 0x1000>;380 };381 dcsr-cpu-sb-proxy@41000 {382 compatible = "fsl,dcsr-e500mc-sb-proxy",383 "fsl,dcsr-cpu-sb-proxy";384 cpu-handle = <&cpu1>;385 reg = <0x41000 0x1000>;386 };387 388=======================================================================389