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1* Power Management Controller2 3Properties:4- compatible: "fsl,<chip>-pmc".5 6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip8 whose PMC is compatible, and implies deep-sleep capability.9 10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip12 whose PMC is compatible, and implies deep-sleep capability.13 14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also16 apply to "fsl,mpc8641d-pmc".17 18 Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these19 bit assignments are indicated via the sleep specifier in each device's20 sleep property.21 22- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource23 is the PMC block, and the second resource is the Clock Configuration24 block.25 26 For devices compatible with "fsl,mpc8548-pmc", the first resource27 is a 32-byte block beginning with DEVDISR.28 29- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first30 resource is the PMC block interrupt.31 32- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,33 this is a phandle to an "fsl,gtm" node on which timer 4 can be used as34 a wakeup source from deep sleep.35 36Sleep specifiers:37 38 fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit39 that is set in the cell, the corresponding bit in SCCR will be saved40 and cleared on suspend, and restored on resume. This sleep controller41 supports disabling and resuming devices at any time.42 43 fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of44 which will be ORed into PMCDR upon suspend, and cleared from PMCDR45 upon resume. The first two cells are as described for fsl,mpc8578-pmc.46 This sleep controller only supports disabling devices during system47 sleep, or permanently.48 49 fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the50 first of which will be ORed into DEVDISR (and the second into51 DEVDISR2, if present -- this cell should be zero or absent if the52 hardware does not have DEVDISR2) upon a request for permanent device53 disabling. This sleep controller does not support configuring devices54 to disable during system sleep (unless supported by another compatible55 match), or dynamically.56 57Example:58 59 power@b00 {60 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";61 reg = <0xb00 0x100 0xa00 0x100>;62 interrupts = <80 8>;63 };64