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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pwm/fsl,vf610-ftm-pwm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale FlexTimer Module (FTM) PWM controller8 9description: |10 The same FTM PWM device can have a different endianness on different SoCs. The11 device tree provides a property to describing this so that an operating system12 device driver can handle all variants of the device. Refer to the table below13 for the endianness of the FTM PWM block as integrated into the existing SoCs:14 15 SoC | FTM-PWM endianness16 --------+-------------------17 Vybrid | LE18 LS1 | BE19 LS2 | LE20 21 Please see ../regmap/regmap.txt for more detail about how to specify endian22 modes in device tree.23 24maintainers:25 - Frank Li <Frank.Li@nxp.com>26 27properties:28 compatible:29 enum:30 - fsl,vf610-ftm-pwm31 - fsl,imx8qm-ftm-pwm32 33 reg:34 maxItems: 135 36 "#pwm-cells":37 const: 338 39 clocks:40 minItems: 441 maxItems: 442 43 clock-names:44 items:45 - const: ftm_sys46 - const: ftm_ext47 - const: ftm_fix48 - const: ftm_cnt_clk_en49 50 pinctrl-0: true51 pinctrl-1: true52 53 pinctrl-names:54 minItems: 155 items:56 - const: default57 - const: sleep58 59 big-endian:60 $ref: /schemas/types.yaml#/definitions/flag61 description:62 Boolean property, required if the FTM PWM registers use a big-63 endian rather than little-endian layout.64 65required:66 - compatible67 - reg68 - clocks69 - clock-names70 71allOf:72 - $ref: pwm.yaml#73 74unevaluatedProperties: false75 76examples:77 - |78 #include <dt-bindings/clock/vf610-clock.h>79 80 pwm@40038000 {81 compatible = "fsl,vf610-ftm-pwm";82 reg = <0x40038000 0x1000>;83 #pwm-cells = <3>;84 clocks = <&clks VF610_CLK_FTM0>,85 <&clks VF610_CLK_FTM0_EXT_SEL>,86 <&clks VF610_CLK_FTM0_FIX_SEL>,87 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;88 clock-names = "ftm_sys", "ftm_ext", "ftm_fix", "ftm_cnt_clk_en";89 pinctrl-names = "default";90 pinctrl-0 = <&pinctrl_pwm0_1>;91 big-endian;92 };93