87 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX PWM controller8 9maintainers:10 - Philipp Zabel <p.zabel@pengutronix.de>11 12allOf:13 - $ref: pwm.yaml#14 15properties:16 "#pwm-cells":17 description:18 The only third cell flag supported by this binding is19 PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.20 const: 321 22 compatible:23 oneOf:24 - enum:25 - fsl,imx1-pwm26 - fsl,imx27-pwm27 - items:28 - enum:29 - fsl,imx25-pwm30 - fsl,imx31-pwm31 - fsl,imx50-pwm32 - fsl,imx51-pwm33 - fsl,imx53-pwm34 - fsl,imx6q-pwm35 - fsl,imx6sl-pwm36 - fsl,imx6sll-pwm37 - fsl,imx6sx-pwm38 - fsl,imx6ul-pwm39 - fsl,imx7d-pwm40 - fsl,imx8mm-pwm41 - fsl,imx8mn-pwm42 - fsl,imx8mp-pwm43 - fsl,imx8mq-pwm44 - fsl,imx8qxp-pwm45 - const: fsl,imx27-pwm46 47 reg:48 maxItems: 149 50 clocks:51 items:52 - description: SoC PWM ipg clock53 - description: SoC PWM per clock54 55 clock-names:56 items:57 - const: ipg58 - const: per59 60 interrupts:61 maxItems: 162 63 power-domains:64 maxItems: 165 66required:67 - compatible68 - reg69 - clocks70 - clock-names71 72additionalProperties: false73 74examples:75 - |76 #include <dt-bindings/clock/imx5-clock.h>77 78 pwm@53fb4000 {79 #pwm-cells = <3>;80 compatible = "fsl,imx27-pwm";81 reg = <0x53fb4000 0x4000>;82 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,83 <&clks IMX5_CLK_PWM1_HF_GATE>;84 clock-names = "ipg", "per";85 interrupts = <61>;86 };87