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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek PWM Controller8 9maintainers:10 - John Crispin <john@phrozen.org>11 12allOf:13 - $ref: pwm.yaml#14 15properties:16 compatible:17 oneOf:18 - enum:19 - mediatek,mt2712-pwm20 - mediatek,mt6795-pwm21 - mediatek,mt7622-pwm22 - mediatek,mt7623-pwm23 - mediatek,mt7628-pwm24 - mediatek,mt7629-pwm25 - mediatek,mt7981-pwm26 - mediatek,mt7986-pwm27 - mediatek,mt7988-pwm28 - mediatek,mt8183-pwm29 - mediatek,mt8365-pwm30 - mediatek,mt8516-pwm31 - items:32 - enum:33 - mediatek,mt8195-pwm34 - const: mediatek,mt8183-pwm35 36 reg:37 maxItems: 138 39 "#pwm-cells":40 const: 241 42 interrupts:43 maxItems: 144 45 clocks:46 minItems: 247 maxItems: 1048 49 clock-names:50 description:51 This controller needs two input clocks for its core and one52 clock for each PWM output.53 minItems: 254 items:55 - const: top56 - const: main57 - const: pwm158 - const: pwm259 - const: pwm360 - const: pwm461 - const: pwm562 - const: pwm663 - const: pwm764 - const: pwm865 66required:67 - compatible68 - reg69 - clocks70 - clock-names71 72additionalProperties: false73 74examples:75 - |76 #include <dt-bindings/interrupt-controller/arm-gic.h>77 #include <dt-bindings/clock/mt2712-clk.h>78 #include <dt-bindings/interrupt-controller/irq.h>79 80 pwm0: pwm@11006000 {81 compatible = "mediatek,mt2712-pwm";82 reg = <0x11006000 0x1000>;83 #pwm-cells = <2>;84 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;85 clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,86 <&pericfg CLK_PERI_PWM0>, <&pericfg CLK_PERI_PWM1>,87 <&pericfg CLK_PERI_PWM2>, <&pericfg CLK_PERI_PWM3>,88 <&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>,89 <&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>;90 clock-names = "top", "main",91 "pwm1", "pwm2",92 "pwm3", "pwm4",93 "pwm5", "pwm6",94 "pwm7", "pwm8";95 };96