96 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra PWFM controller8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13properties:14 compatible:15 oneOf:16 - enum:17 - nvidia,tegra20-pwm18 - nvidia,tegra186-pwm19 20 - items:21 - enum:22 - nvidia,tegra30-pwm23 - nvidia,tegra114-pwm24 - nvidia,tegra124-pwm25 - nvidia,tegra132-pwm26 - nvidia,tegra210-pwm27 - enum:28 - nvidia,tegra20-pwm29 30 - items:31 - const: nvidia,tegra194-pwm32 - const: nvidia,tegra186-pwm33 34 - items:35 - const: nvidia,tegra234-pwm36 - const: nvidia,tegra194-pwm37 38 reg:39 maxItems: 140 41 clocks:42 maxItems: 143 44 resets:45 items:46 - description: module reset47 48 reset-names:49 items:50 - const: pwm51 52 "#pwm-cells":53 const: 254 55 pinctrl-names:56 items:57 - const: default58 - const: sleep59 60 pinctrl-0:61 description: configuration for the default/active state62 63 pinctrl-1:64 description: configuration for the sleep state65 66 operating-points-v2: true67 68 power-domains:69 items:70 - description: phandle to the core power domain71 72allOf:73 - $ref: pwm.yaml74 75required:76 - compatible77 - reg78 - clocks79 - resets80 - reset-names81 82additionalProperties: false83 84examples:85 - |86 #include <dt-bindings/clock/tegra20-car.h>87 88 pwm: pwm@7000a000 {89 compatible = "nvidia,tegra20-pwm";90 reg = <0x7000a000 0x100>;91 #pwm-cells = <2>;92 clocks = <&tegra_car TEGRA20_CLK_PWM>;93 resets = <&tegra_car 17>;94 reset-names = "pwm";95 };96