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1NXP LPC1850 Reset Generation Unit (RGU)2========================================3 4Please also refer to reset.txt in this directory for common reset5controller binding usage.6 7Required properties:8- compatible: Should be "nxp,lpc1850-rgu"9- reg: register base and length10- clocks: phandle and clock specifier to RGU clocks11- clock-names: should contain "delay" and "reg"12- #reset-cells: should be 113 14See table below for valid peripheral reset numbers. Numbers not15in the table below are either reserved or not applicable for16normal operation.17 18Reset Peripheral19 9 System control unit (SCU)20 12 ARM Cortex-M0 subsystem core (LPC43xx only)21 13 CPU core22 16 LCD controller23 17 USB024 18 USB125 19 DMA26 20 SDIO27 21 External memory controller (EMC)28 22 Ethernet29 25 Flash bank A30 27 EEPROM31 28 GPIO32 29 Flash bank B33 32 Timer034 33 Timer135 34 Timer236 35 Timer337 36 Repetitive Interrupt timer (RIT)38 37 State Configurable Timer (SCT)39 38 Motor control PWM (MCPWM)40 39 QEI41 40 ADC042 41 ADC143 42 DAC44 44 USART045 45 UART146 46 USART247 47 USART348 48 I2C049 49 I2C150 50 SSP051 51 SSP152 52 I2S0 and I2S153 53 Serial Flash Interface (SPIFI)54 54 C_CAN155 55 C_CAN056 56 ARM Cortex-M0 application core (LPC4370 only)57 57 SGPIO (LPC43xx only)58 58 SPI (LPC43xx only)59 60 ADCHS (12-bit ADC) (LPC4370 only)60 61Refer to NXP LPC18xx or LPC43xx user manual for more details about62the reset signals and the connected block/peripheral.63 64Reset provider example:65rgu: reset-controller@40053000 {66 compatible = "nxp,lpc1850-rgu";67 reg = <0x40053000 0x1000>;68 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;69 clock-names = "delay", "reg";70 #reset-cells = <1>;71};72 73Reset consumer example:74mac: ethernet@40010000 {75 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";76 reg = <0x40010000 0x2000>;77 interrupts = <5>;78 interrupt-names = "macirq";79 clocks = <&ccu1 CLK_CPU_ETHERNET>;80 clock-names = "stmmaceth";81 resets = <&rgu 22>;82 reset-names = "stmmaceth";83};84