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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/{G2L,V2L} USBPHY Control8 9maintainers:10 - Biju Das <biju.das.jz@bp.renesas.com>11 12description:13 The RZ/G2L USBPHY Control mainly controls reset and power down of the14 USB/PHY.15 16properties:17 compatible:18 items:19 - enum:20 - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five21 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}22 - renesas,r9a07g054-usbphy-ctrl # RZ/V2L23 - const: renesas,rzg2l-usbphy-ctrl24 25 reg:26 maxItems: 127 28 clocks:29 maxItems: 130 31 resets:32 maxItems: 133 34 power-domains:35 maxItems: 136 37 '#reset-cells':38 const: 139 description: |40 The phandle's argument in the reset specifier is the PHY reset associated41 with the USB port.42 0 = Port 1 Phy reset43 1 = Port 2 Phy reset44 45 regulator-vbus:46 type: object47 description: USB VBUS regulator48 $ref: /schemas/regulator/regulator.yaml#49 unevaluatedProperties: false50 51required:52 - compatible53 - reg54 - clocks55 - resets56 - power-domains57 - '#reset-cells'58 - regulator-vbus59 60additionalProperties: false61 62examples:63 - |64 #include <dt-bindings/clock/r9a07g044-cpg.h>65 66 phyrst: usbphy-ctrl@11c40000 {67 compatible = "renesas,r9a07g044-usbphy-ctrl",68 "renesas,rzg2l-usbphy-ctrl";69 reg = <0x11c40000 0x10000>;70 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;71 resets = <&cpg R9A07G044_USB_PRESETN>;72 power-domains = <&cpg>;73 #reset-cells = <1>;74 regulator-vbus {75 regulator-name = "vbus";76 };77 };78