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1Xilinx Zynq Reset Manager2 3The Zynq AP-SoC has several different resets.4 5See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.6 7Required properties:8- compatible: "xlnx,zynq-reset"9- reg: SLCR offset and size taken via syscon <0x200 0x48>10- syscon: <&slcr>11 This should be a phandle to the Zynq's SLCR registers.12- #reset-cells: Must be 113 14The Zynq Reset Manager needs to be a childnode of the SLCR.15 16Example:17 rstc: rstc@200 {18 compatible = "xlnx,zynq-reset";19 reg = <0x200 0x48>;20 #reset-cells = <1>;21 syscon = <&slcr>;22 };23 24Reset outputs:25 0 : soft reset26 32 : ddr reset27 64 : topsw reset28 96 : dmac reset29 128: usb0 reset30 129: usb1 reset31 160: gem0 reset32 161: gem1 reset33 164: gem0 rx reset34 165: gem1 rx reset35 166: gem0 ref reset36 167: gem1 ref reset37 192: sdio0 reset38 193: sdio1 reset39 196: sdio0 ref reset40 197: sdio1 ref reset41 224: spi0 reset42 225: spi1 reset43 226: spi0 ref reset44 227: spi1 ref reset45 256: can0 reset46 257: can1 reset47 258: can0 ref reset48 259: can1 ref reset49 288: i2c0 reset50 289: i2c1 reset51 320: uart0 reset52 321: uart1 reset53 322: uart0 ref reset54 323: uart1 ref reset55 352: gpio reset56 384: lqspi reset57 385: qspi ref reset58 416: smc reset59 417: smc ref reset60 448: ocm reset61 512: fpga0 out reset62 513: fpga1 out reset63 514: fpga2 out reset64 515: fpga3 out reset65 544: a9 reset 066 545: a9 reset 167 552: peri reset68 69