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1# SPDX-License-Identifier: (GPL-2.0 OR MIT)2%YAML 1.23---4$id: http://devicetree.org/schemas/riscv/cpus.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: RISC-V CPUs8 9maintainers:10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>13 14description: |15 This document uses some terminology common to the RISC-V community16 that is not widely used, the definitions of which are listed here:17 18 hart: A hardware execution context, which contains all the state19 mandated by the RISC-V ISA: a PC and some registers. This20 terminology is designed to disambiguate software's view of execution21 contexts from any particular microarchitectural implementation22 strategy. For example, an Intel laptop containing one socket with23 two cores, each of which has two hyperthreads, could be described as24 having four harts.25 26allOf:27 - $ref: /schemas/cpu.yaml#28 - $ref: extensions.yaml29 30properties:31 compatible:32 oneOf:33 - items:34 - enum:35 - amd,mbv3236 - andestech,ax45mp37 - canaan,k21038 - sifive,bullet039 - sifive,e540 - sifive,e741 - sifive,e7142 - sifive,rocket043 - sifive,s744 - sifive,u545 - sifive,u5446 - sifive,u747 - sifive,u7448 - sifive,u74-mc49 - thead,c90650 - thead,c90851 - thead,c91052 - thead,c92053 - const: riscv54 - items:55 - enum:56 - sifive,e5157 - sifive,u54-mc58 - const: sifive,rocket059 - const: riscv60 - const: riscv # Simulator only61 description:62 Identifies that the hart uses the RISC-V instruction set63 and identifies the type of the hart.64 65 mmu-type:66 description:67 Identifies the largest MMU address translation mode supported by68 this hart. These values originate from the RISC-V Privileged69 Specification document, available from70 https://riscv.org/specifications/71 $ref: /schemas/types.yaml#/definitions/string72 enum:73 - riscv,sv3274 - riscv,sv3975 - riscv,sv4876 - riscv,sv5777 - riscv,none78 79 reg:80 description:81 The hart ID of this CPU node.82 83 riscv,cbom-block-size:84 $ref: /schemas/types.yaml#/definitions/uint3285 description:86 The blocksize in bytes for the Zicbom cache operations.87 88 riscv,cbop-block-size:89 $ref: /schemas/types.yaml#/definitions/uint3290 description:91 The blocksize in bytes for the Zicbop cache operations.92 93 riscv,cboz-block-size:94 $ref: /schemas/types.yaml#/definitions/uint3295 description:96 The blocksize in bytes for the Zicboz cache operations.97 98 # RISC-V has multiple properties for cache op block sizes as the sizes99 # differ between individual CBO extensions100 cache-op-block-size: false101 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here102 timebase-frequency: false103 104 interrupt-controller:105 type: object106 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#107 108 cpu-idle-states:109 $ref: /schemas/types.yaml#/definitions/phandle-array110 items:111 maxItems: 1112 description: |113 List of phandles to idle state nodes supported114 by this hart (see ./idle-states.yaml).115 116 capacity-dmips-mhz:117 description:118 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in119 DMIPS/MHz, relative to highest capacity-dmips-mhz120 in the system.121 122anyOf:123 - required:124 - riscv,isa125 - required:126 - riscv,isa-base127 128dependencies:129 riscv,isa-base: [ "riscv,isa-extensions" ]130 riscv,isa-extensions: [ "riscv,isa-base" ]131 132required:133 - interrupt-controller134 135unevaluatedProperties: false136 137examples:138 - |139 // Example 1: SiFive Freedom U540G Development Kit140 cpus {141 #address-cells = <1>;142 #size-cells = <0>;143 timebase-frequency = <1000000>;144 cpu@0 {145 clock-frequency = <0>;146 compatible = "sifive,rocket0", "riscv";147 device_type = "cpu";148 i-cache-block-size = <64>;149 i-cache-sets = <128>;150 i-cache-size = <16384>;151 reg = <0>;152 riscv,isa-base = "rv64i";153 riscv,isa-extensions = "i", "m", "a", "c";154 155 cpu_intc0: interrupt-controller {156 #interrupt-cells = <1>;157 compatible = "riscv,cpu-intc";158 interrupt-controller;159 };160 };161 cpu@1 {162 clock-frequency = <0>;163 compatible = "sifive,rocket0", "riscv";164 d-cache-block-size = <64>;165 d-cache-sets = <64>;166 d-cache-size = <32768>;167 d-tlb-sets = <1>;168 d-tlb-size = <32>;169 device_type = "cpu";170 i-cache-block-size = <64>;171 i-cache-sets = <64>;172 i-cache-size = <32768>;173 i-tlb-sets = <1>;174 i-tlb-size = <32>;175 mmu-type = "riscv,sv39";176 reg = <1>;177 tlb-split;178 riscv,isa-base = "rv64i";179 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";180 181 cpu_intc1: interrupt-controller {182 #interrupt-cells = <1>;183 compatible = "riscv,cpu-intc";184 interrupt-controller;185 };186 };187 };188 189 - |190 // Example 2: Spike ISA Simulator with 1 Hart191 cpus {192 #address-cells = <1>;193 #size-cells = <0>;194 cpu@0 {195 device_type = "cpu";196 reg = <0>;197 compatible = "riscv";198 mmu-type = "riscv,sv48";199 riscv,isa-base = "rv64i";200 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";201 202 interrupt-controller {203 #interrupt-cells = <1>;204 interrupt-controller;205 compatible = "riscv,cpu-intc";206 };207 };208 };209...210