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1# SPDX-License-Identifier: (GPL-2.0 OR MIT)2%YAML 1.23---4$id: http://devicetree.org/schemas/riscv/extensions.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: RISC-V ISA extensions8 9maintainers:10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>13 14description: |15 RISC-V has a large number of extensions, some of which are "standard"16 extensions, meaning they are ratified by RISC-V International, and others17 are "vendor" extensions.18 This document defines properties that indicate whether a hart supports a19 given extension.20 21 Once a standard extension has been ratified, no changes in behaviour can be22 made without the creation of a new extension.23 The properties for standard extensions therefore map to their originally24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.25 See the "i" property for more information.26 27select:28 properties:29 compatible:30 contains:31 const: riscv32 33properties:34 riscv,isa:35 description:36 Identifies the specific RISC-V instruction set architecture37 supported by the hart. These are documented in the RISC-V38 User-Level ISA document, available from39 https://riscv.org/specifications/40 41 Due to revisions of the ISA specification, some deviations42 have arisen over time.43 Notably, riscv,isa was defined prior to the creation of the44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"45 implies "zicntr_zicsr_zifencei_zihpm".46 47 While the isa strings in ISA specification are case48 insensitive, letters in the riscv,isa string must be all49 lowercase.50 $ref: /schemas/types.yaml#/definitions/string51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$52 deprecated: true53 54 riscv,isa-base:55 description:56 The base ISA implemented by this hart, as described by the 2019121357 version of the unprivileged ISA specification.58 enum:59 - rv32i60 - rv64i61 62 riscv,isa-extensions:63 $ref: /schemas/types.yaml#/definitions/string-array64 minItems: 165 description: Extensions supported by the hart.66 items:67 anyOf:68 # single letter extensions, in canonical order69 - const: i70 description: |71 The base integer instruction set, as ratified in the 2019121372 version of the unprivileged ISA specification.73 74 This does not include Chapter 10, "Counters", which was moved into75 the Zicntr and Zihpm extensions after the ratification of the76 20191213 version of the unprivileged specification.77 78 - const: m79 description:80 The standard M extension for integer multiplication and division, as81 ratified in the 20191213 version of the unprivileged ISA82 specification.83 84 - const: a85 description:86 The standard A extension for atomic instructions, as ratified in the87 20191213 version of the unprivileged ISA specification.88 89 - const: f90 description:91 The standard F extension for single-precision floating point, as92 ratified in the 20191213 version of the unprivileged ISA93 specification.94 95 - const: d96 description:97 The standard D extension for double-precision floating-point, as98 ratified in the 20191213 version of the unprivileged ISA99 specification.100 101 - const: q102 description:103 The standard Q extension for quad-precision floating-point, as104 ratified in the 20191213 version of the unprivileged ISA105 specification.106 107 - const: c108 description:109 The standard C extension for compressed instructions, as ratified in110 the 20191213 version of the unprivileged ISA specification.111 112 - const: v113 description:114 The standard V extension for vector operations, as ratified115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f116 encoding") of the riscv-v-spec.117 118 - const: h119 description:120 The standard H extension for hypervisors as ratified in the 20191213121 version of the privileged ISA specification.122 123 # multi-letter extensions, sorted alphanumerically124 - const: smaia125 description: |126 The standard Smaia supervisor-level extension for the advanced127 interrupt architecture for machine-mode-visible csr and behavioural128 changes to interrupts as frozen at commit ccbddab ("Merge pull129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.130 131 - const: smstateen132 description: |133 The standard Smstateen extension for controlling access to CSRs134 added by other RISC-V extensions in H/S/VS/U/VU modes and as135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.136 137 - const: ssaia138 description: |139 The standard Ssaia supervisor-level extension for the advanced140 interrupt architecture for supervisor-mode-visible csr and141 behavioural changes to interrupts as frozen at commit ccbddab142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.143 144 - const: sscofpmf145 description: |146 The standard Sscofpmf supervisor-level extension for count overflow147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability148 to manually trigger workflow. (#2)") of riscv-count-overflow.149 150 - const: sstc151 description: |152 The standard Sstc supervisor-level extension for time compare as153 ratified at commit 3f9ed34 ("Add ability to manually trigger154 workflow. (#2)") of riscv-time-compare.155 156 - const: svinval157 description:158 The standard Svinval supervisor-level extension for fine-grained159 address-translation cache invalidation as ratified in the 20191213160 version of the privileged ISA specification.161 162 - const: svnapot163 description:164 The standard Svnapot supervisor-level extensions for napot165 translation contiguity as ratified in the 20191213 version of the166 privileged ISA specification.167 168 - const: svpbmt169 description:170 The standard Svpbmt supervisor-level extensions for page-based171 memory types as ratified in the 20191213 version of the privileged172 ISA specification.173 174 - const: svvptc175 description:176 The standard Svvptc supervisor-level extension for177 address-translation cache behaviour with respect to invalid entries178 as ratified at commit 4a69197e5617 ("Update to ratified state") of179 riscv-svvptc.180 181 - const: zacas182 description: |183 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions184 is supported as ratified at commit 5059e0ca641c ("update to185 ratified") of the riscv-zacas.186 187 - const: zawrs188 description: |189 The Zawrs extension for entering a low-power state or for trapping190 to a hypervisor while waiting on a store to a memory location, as191 ratified in commit 98918c844281 ("Merge pull request #1217 from192 riscv/zawrs") of riscv-isa-manual.193 194 - const: zba195 description: |196 The standard Zba bit-manipulation extension for address generation197 acceleration instructions as ratified at commit 6d33919 ("Merge pull198 request #158 from hirooih/clmul-fix-loop-end-condition") of199 riscv-bitmanip.200 201 - const: zbb202 description: |203 The standard Zbb bit-manipulation extension for basic bit-manipulation204 as ratified at commit 6d33919 ("Merge pull request #158 from205 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.206 207 - const: zbc208 description: |209 The standard Zbc bit-manipulation extension for carry-less210 multiplication as ratified at commit 6d33919 ("Merge pull request211 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.212 213 - const: zbkb214 description:215 The standard Zbkb bitmanip instructions for cryptography as ratified216 in version 1.0 of RISC-V Cryptography Extensions Volume I217 specification.218 219 - const: zbkc220 description:221 The standard Zbkc carry-less multiply instructions as ratified222 in version 1.0 of RISC-V Cryptography Extensions Volume I223 specification.224 225 - const: zbkx226 description:227 The standard Zbkx crossbar permutation instructions as ratified228 in version 1.0 of RISC-V Cryptography Extensions Volume I229 specification.230 231 - const: zbs232 description: |233 The standard Zbs bit-manipulation extension for single-bit234 instructions as ratified at commit 6d33919 ("Merge pull request #158235 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.236 237 - const: zca238 description: |239 The Zca extension part of Zc* standard extensions for code size240 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on241 RV64 as it contains no instructions") of riscv-code-size-reduction,242 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed243 of zc.adoc to src tree.").244 245 - const: zcb246 description: |247 The Zcb extension part of Zc* standard extensions for code size248 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on249 RV64 as it contains no instructions") of riscv-code-size-reduction,250 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed251 of zc.adoc to src tree.").252 253 - const: zcd254 description: |255 The Zcd extension part of Zc* standard extensions for code size256 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on257 RV64 as it contains no instructions") of riscv-code-size-reduction,258 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed259 of zc.adoc to src tree.").260 261 - const: zcf262 description: |263 The Zcf extension part of Zc* standard extensions for code size264 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on265 RV64 as it contains no instructions") of riscv-code-size-reduction,266 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed267 of zc.adoc to src tree.").268 269 - const: zcmop270 description:271 The standard Zcmop extension version 1.0, as ratified in commit272 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.273 274 - const: zfa275 description:276 The standard Zfa extension for additional floating point277 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of278 riscv-isa-manual.279 280 - const: zfh281 description:282 The standard Zfh extension for 16-bit half-precision binary283 floating-point instructions, as ratified in commit 64074bc ("Update284 version numbers for Zfh/Zfinx") of riscv-isa-manual.285 286 - const: zfhmin287 description:288 The standard Zfhmin extension which provides minimal support for289 16-bit half-precision binary floating-point instructions, as ratified290 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of291 riscv-isa-manual.292 293 - const: zk294 description:295 The standard Zk Standard Scalar cryptography extension as ratified296 in version 1.0 of RISC-V Cryptography Extensions Volume I297 specification.298 299 - const: zkn300 description:301 The standard Zkn NIST algorithm suite extensions as ratified in302 version 1.0 of RISC-V Cryptography Extensions Volume I303 specification.304 305 - const: zknd306 description: |307 The standard Zknd for NIST suite: AES decryption instructions as308 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I309 specification.310 311 - const: zkne312 description: |313 The standard Zkne for NIST suite: AES encryption instructions as314 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I315 specification.316 317 - const: zknh318 description: |319 The standard Zknh for NIST suite: hash function instructions as320 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I321 specification.322 323 - const: zkr324 description:325 The standard Zkr entropy source extension as ratified in version326 1.0 of RISC-V Cryptography Extensions Volume I specification.327 This string being present means that the CSR associated to this328 extension is accessible at the privilege level to which that329 device-tree has been provided.330 331 - const: zks332 description:333 The standard Zks ShangMi algorithm suite extensions as ratified in334 version 1.0 of RISC-V Cryptography Extensions Volume I335 specification.336 337 - const: zksed338 description: |339 The standard Zksed for ShangMi suite: SM4 block cipher instructions340 as ratified in version 1.0 of RISC-V Cryptography Extensions341 Volume I specification.342 343 - const: zksh344 description: |345 The standard Zksh for ShangMi suite: SM3 hash function instructions346 as ratified in version 1.0 of RISC-V Cryptography Extensions347 Volume I specification.348 349 - const: zkt350 description:351 The standard Zkt for data independent execution latency as ratified352 in version 1.0 of RISC-V Cryptography Extensions Volume I353 specification.354 355 - const: zicbom356 description:357 The standard Zicbom extension for base cache management operations as358 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.359 360 - const: zicbop361 description:362 The standard Zicbop extension for cache-block prefetch instructions363 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of364 riscv-CMOs.365 366 - const: zicboz367 description:368 The standard Zicboz extension for cache-block zeroing as ratified369 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.370 371 - const: zicntr372 description:373 The standard Zicntr extension for base counters and timers, as374 ratified in the 20191213 version of the unprivileged ISA375 specification.376 377 - const: zicond378 description:379 The standard Zicond extension for conditional arithmetic and380 conditional-select/move operations as ratified in commit 95cf1f9381 ("Add changes requested by Ved during signoff") of riscv-zicond.382 383 - const: zicsr384 description: |385 The standard Zicsr extension for control and status register386 instructions, as ratified in the 20191213 version of the387 unprivileged ISA specification.388 389 This does not include Chapter 10, "Counters", which documents390 special case read-only CSRs, that were moved into the Zicntr and391 Zihpm extensions after the ratification of the 20191213 version of392 the unprivileged specification.393 394 - const: zifencei395 description:396 The standard Zifencei extension for instruction-fetch fence, as397 ratified in the 20191213 version of the unprivileged ISA398 specification.399 400 - const: zihintpause401 description:402 The standard Zihintpause extension for pause hints, as ratified in403 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.404 405 - const: zihintntl406 description:407 The standard Zihintntl extension for non-temporal locality hints, as408 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the409 riscv-isa-manual.410 411 - const: zihpm412 description:413 The standard Zihpm extension for hardware performance counters, as414 ratified in the 20191213 version of the unprivileged ISA415 specification.416 417 - const: zimop418 description:419 The standard Zimop extension version 1.0, as ratified in commit420 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.421 422 - const: ztso423 description:424 The standard Ztso extension for total store ordering, as ratified425 in commit 2e5236 ("Ztso is now ratified.") of the426 riscv-isa-manual.427 428 - const: zvbb429 description:430 The standard Zvbb extension for vectored basic bit-manipulation431 instructions, as ratified in commit 56ed795 ("Update432 riscv-crypto-spec-vector.adoc") of riscv-crypto.433 434 - const: zvbc435 description:436 The standard Zvbc extension for vectored carryless multiplication437 instructions, as ratified in commit 56ed795 ("Update438 riscv-crypto-spec-vector.adoc") of riscv-crypto.439 440 - const: zve32f441 description:442 The standard Zve32f extension for embedded processors, as ratified443 in commit 6f702a2 ("Vector extensions are now ratified") of444 riscv-v-spec.445 446 - const: zve32x447 description:448 The standard Zve32x extension for embedded processors, as ratified449 in commit 6f702a2 ("Vector extensions are now ratified") of450 riscv-v-spec.451 452 - const: zve64d453 description:454 The standard Zve64d extension for embedded processors, as ratified455 in commit 6f702a2 ("Vector extensions are now ratified") of456 riscv-v-spec.457 458 - const: zve64f459 description:460 The standard Zve64f extension for embedded processors, as ratified461 in commit 6f702a2 ("Vector extensions are now ratified") of462 riscv-v-spec.463 464 - const: zve64x465 description:466 The standard Zve64x extension for embedded processors, as ratified467 in commit 6f702a2 ("Vector extensions are now ratified") of468 riscv-v-spec.469 470 - const: zvfh471 description:472 The standard Zvfh extension for vectored half-precision473 floating-point instructions, as ratified in commit e2ccd05474 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.475 476 - const: zvfhmin477 description:478 The standard Zvfhmin extension for vectored minimal half-precision479 floating-point instructions, as ratified in commit e2ccd05480 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.481 482 - const: zvkb483 description:484 The standard Zvkb extension for vector cryptography bit-manipulation485 instructions, as ratified in commit 56ed795 ("Update486 riscv-crypto-spec-vector.adoc") of riscv-crypto.487 488 - const: zvkg489 description:490 The standard Zvkg extension for vector GCM/GMAC instructions, as491 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")492 of riscv-crypto.493 494 - const: zvkn495 description:496 The standard Zvkn extension for NIST algorithm suite instructions, as497 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")498 of riscv-crypto.499 500 - const: zvknc501 description:502 The standard Zvknc extension for NIST algorithm suite with carryless503 multiply instructions, as ratified in commit 56ed795 ("Update504 riscv-crypto-spec-vector.adoc") of riscv-crypto.505 506 - const: zvkned507 description:508 The standard Zvkned extension for Vector AES block cipher509 instructions, as ratified in commit 56ed795 ("Update510 riscv-crypto-spec-vector.adoc") of riscv-crypto.511 512 - const: zvkng513 description:514 The standard Zvkng extension for NIST algorithm suite with GCM515 instructions, as ratified in commit 56ed795 ("Update516 riscv-crypto-spec-vector.adoc") of riscv-crypto.517 518 - const: zvknha519 description: |520 The standard Zvknha extension for NIST suite: vector SHA-2 secure,521 hash (SHA-256 only) instructions, as ratified in commit522 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.523 524 - const: zvknhb525 description: |526 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,527 hash (SHA-256 and SHA-512) instructions, as ratified in commit528 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.529 530 - const: zvks531 description:532 The standard Zvks extension for ShangMi algorithm suite533 instructions, as ratified in commit 56ed795 ("Update534 riscv-crypto-spec-vector.adoc") of riscv-crypto.535 536 - const: zvksc537 description:538 The standard Zvksc extension for ShangMi algorithm suite with539 carryless multiplication instructions, as ratified in commit 56ed795540 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.541 542 - const: zvksed543 description: |544 The standard Zvksed extension for ShangMi suite: SM4 block cipher545 instructions, as ratified in commit 56ed795 ("Update546 riscv-crypto-spec-vector.adoc") of riscv-crypto.547 548 - const: zvksh549 description: |550 The standard Zvksh extension for ShangMi suite: SM3 secure hash551 instructions, as ratified in commit 56ed795 ("Update552 riscv-crypto-spec-vector.adoc") of riscv-crypto.553 554 - const: zvksg555 description:556 The standard Zvksg extension for ShangMi algorithm suite with GCM557 instructions, as ratified in commit 56ed795 ("Update558 riscv-crypto-spec-vector.adoc") of riscv-crypto.559 560 - const: zvkt561 description:562 The standard Zvkt extension for vector data-independent execution563 latency, as ratified in commit 56ed795 ("Update564 riscv-crypto-spec-vector.adoc") of riscv-crypto.565 566 - const: xandespmu567 description:568 The Andes Technology performance monitor extension for counter overflow569 and privilege mode filtering. For more details, see Counter Related570 Registers in the AX45MP datasheet.571 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf572 573 allOf:574 # Zcb depends on Zca575 - if:576 contains:577 const: zcb578 then:579 contains:580 const: zca581 # Zcd depends on Zca and D582 - if:583 contains:584 const: zcd585 then:586 allOf:587 - contains:588 const: zca589 - contains:590 const: d591 # Zcf depends on Zca and F592 - if:593 contains:594 const: zcf595 then:596 allOf:597 - contains:598 const: zca599 - contains:600 const: f601 # Zcmop depends on Zca602 - if:603 contains:604 const: zcmop605 then:606 contains:607 const: zca608 609allOf:610 # Zcf extension does not exist on rv64611 - if:612 properties:613 riscv,isa-extensions:614 contains:615 const: zcf616 riscv,isa-base:617 contains:618 const: rv64i619 then:620 properties:621 riscv,isa-extensions:622 not:623 contains:624 const: zcf625 626additionalProperties: true627...628