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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries3%YAML 1.24---5$id: http://devicetree.org/schemas/rtc/atmel,at91sam9260-rtt.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Atmel AT91 RTT9 10allOf:11 - $ref: rtc.yaml#12 13maintainers:14 - Alexandre Belloni <alexandre.belloni@bootlin.com>15 16properties:17 compatible:18 oneOf:19 - items:20 - const: atmel,at91sam9260-rtt21 - items:22 - enum:23 - microchip,sam9x60-rtt24 - microchip,sam9x7-rtt25 - const: atmel,at91sam9260-rtt26 - items:27 - const: microchip,sama7g5-rtt28 - const: microchip,sam9x60-rtt29 - const: atmel,at91sam9260-rtt30 31 reg:32 maxItems: 133 34 interrupts:35 maxItems: 136 37 clocks:38 maxItems: 139 40 atmel,rtt-rtc-time-reg:41 $ref: /schemas/types.yaml#/definitions/phandle-array42 items:43 - items:44 - description: Phandle to the GPBR node.45 - description: Offset within the GPBR block.46 description:47 Should encode the GPBR register used to store the time base when the48 RTT is used as an RTC. The first cell should point to the GPBR node49 and the second one encodes the offset within the GPBR block (or in50 other words, the GPBR register used to store the time base).51 52required:53 - compatible54 - reg55 - interrupts56 - clocks57 - atmel,rtt-rtc-time-reg58 59unevaluatedProperties: false60 61examples:62 - |63 #include <dt-bindings/interrupt-controller/irq.h>64 65 rtc@fffffd20 {66 compatible = "atmel,at91sam9260-rtt";67 reg = <0xfffffd20 0x10>;68 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;69 clocks = <&clk32k>;70 atmel,rtt-rtc-time-reg = <&gpbr 0x0>;71 };72