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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock8 9description:10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.11 The RTC controller has separate IRQ lines for seconds and alarm.12 13maintainers:14 - Michal Simek <michal.simek@amd.com>15 16allOf:17 - $ref: rtc.yaml#18 19properties:20 compatible:21 oneOf:22 - const: xlnx,zynqmp-rtc23 - items:24 - enum:25 - xlnx,versal-rtc26 - xlnx,versal-net-rtc27 - const: xlnx,zynqmp-rtc28 29 reg:30 maxItems: 131 32 clocks:33 maxItems: 134 35 clock-names:36 items:37 - const: rtc38 39 interrupts:40 maxItems: 241 42 interrupt-names:43 items:44 - const: alarm45 - const: sec46 47 calibration:48 description: |49 calibration value for 1 sec period which will50 be programmed directly to calibration register.51 $ref: /schemas/types.yaml#/definitions/uint3252 minimum: 0x153 maximum: 0x1FFFFF54 default: 0x19823355 deprecated: true56 57 power-domains:58 maxItems: 159 60required:61 - compatible62 - reg63 - interrupts64 - interrupt-names65 66additionalProperties: false67 68examples:69 - |70 soc {71 #address-cells = <2>;72 #size-cells = <2>;73 74 rtc: rtc@ffa60000 {75 compatible = "xlnx,zynqmp-rtc";76 reg = <0x0 0xffa60000 0x0 0x100>;77 interrupt-parent = <&gic>;78 interrupts = <0 26 4>, <0 27 4>;79 interrupt-names = "alarm", "sec";80 calibration = <0x198233>;81 clock-names = "rtc";82 clocks = <&rtc_clk>;83 };84 };85