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1* HiSilicon SAS controller2 3The HiSilicon SAS controller supports SAS/SATA.4 5Main node required properties:6 - compatible : value should be as follows:7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset10 - sas-addr : array of 8 bytes for host SAS address11 - reg : Contains two regions. The first is the address and length of the SAS12 register. The second is the address and length of CPLD register for13 SGPIO control. The second is optional, and should be set only when14 we use a CPLD for directly attached disk LED control.15 - hisilicon,sas-syscon: phandle of syscon used for sas control16 - ctrl-reset-reg : offset to controller reset register in ctrl reg17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg19 - queue-count : number of delivery and completion queues in the controller20 - phy-count : number of phys accessible by the controller21 - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal22 sources; the interrupts are ordered in 3 groups, as follows:23 - Phy interrupts24 - Completion queue interrupts25 - Fatal interrupts26 Phy interrupts : Each phy has 3 interrupt sources:27 - broadcast28 - phyup29 - abnormal30 The phy interrupts are ordered into groups of 3 per phy31 (broadcast, phyup, and abnormal) in increasing order.32 Completion queue interrupts : each completion queue has 133 interrupt source.34 The interrupts are ordered in increasing order.35 Fatal interrupts : the fatal interrupts are ordered as follows:36 - ECC37 - AXI bus38 For v2 hw: Interrupts for phys, Sata, and completion queues;39 the interrupts are ordered in 3 groups, as follows:40 - Phy interrupts41 - Sata interrupts42 - Completion queue interrupts43 Phy interrupts : Each controller has 2 phy interrupts:44 - phy up/down45 - channel interrupt46 Sata interrupts : Each phy on the controller has 1 Sata47 interrupt. The interrupts are ordered in increasing48 order.49 Completion queue interrupts : each completion queue has 150 interrupt source. The interrupts are ordered in51 increasing order.52 53Optional main node properties:54 - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the55 "am-max-transmissions" limitation.56 - hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis,57 preshoot, and boost attenuation readings for the board. They58 are used to describe the signal attenuation of the board. These59 values' range is 7600 to 12400, and used to represent -24dB to60 24dB.61 The formula is "y = (x-10000)/10000". For example, 1047862 means 4.78dB.63 64Example:65 sas0: sas@c1000000 {66 compatible = "hisilicon,hip05-sas-v1";67 sas-addr = [50 01 88 20 16 00 00 0a];68 reg = <0x0 0xc1000000 0x0 0x10000>;69 hisilicon,sas-syscon = <&pcie_sas>;70 ctrl-reset-reg = <0xa60>;71 ctrl-reset-sts-reg = <0x5a30>;72 ctrl-clock-ena-reg = <0x338>;73 queue-count = <32>;74 phy-count = <8>;75 dma-coherent;76 interrupt-parent = <&mbigen_dsa>;77 interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */78 <269 4>,<273 4>,<274 4>,/* phy1 */79 <279 4>,<283 4>,<284 4>,/* phy2 */80 <289 4>,<293 4>,<294 4>,/* phy3 */81 <299 4>,<303 4>,<304 4>,/* phy4 */82 <309 4>,<313 4>,<314 4>,/* phy5 */83 <319 4>,<323 4>,<324 4>,/* phy6 */84 <329 4>,<333 4>,<334 4>,/* phy7 */85 <336 1>,<337 1>,<338 1>,/* cq0-2 */86 <339 1>,<340 1>,<341 1>,/* cq3-5 */87 <342 1>,<343 1>,<344 1>,/* cq6-8 */88 <345 1>,<346 1>,<347 1>,/* cq9-11 */89 <348 1>,<349 1>,<350 1>,/* cq12-14 */90 <351 1>,<352 1>,<353 1>,/* cq15-17 */91 <354 1>,<355 1>,<356 1>,/* cq18-20 */92 <357 1>,<358 1>,<359 1>,/* cq21-23 */93 <360 1>,<361 1>,<362 1>,/* cq24-26 */94 <363 1>,<364 1>,<365 1>,/* cq27-29 */95 <366 1>,<367 1>/* cq30-31 */96 <376 4>,/* fatal ecc */97 <381 4>;/* fatal axi */98 };99