265 lines · yaml
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>2%YAML 1.23---4$id: http://devicetree.org/schemas/serial/8250.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: UART (Universal Asynchronous Receiver/Transmitter)8 9maintainers:10 - devicetree@vger.kernel.org11 12allOf:13 - $ref: serial.yaml#14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#15 - if:16 anyOf:17 - required:18 - aspeed,lpc-io-reg19 - required:20 - aspeed,lpc-interrupts21 - required:22 - aspeed,sirq-polarity-sense23 then:24 properties:25 compatible:26 const: aspeed,ast2500-vuart27 - if:28 properties:29 compatible:30 const: mrvl,mmp-uart31 then:32 properties:33 reg-shift:34 const: 235 required:36 - reg-shift37 - if:38 not:39 properties:40 compatible:41 items:42 - enum:43 - ns825044 - ns1645045 - ns1655046 - ns16550a47 then:48 anyOf:49 - required: [ clock-frequency ]50 - required: [ clocks ]51 52properties:53 compatible:54 oneOf:55 - const: ns825056 - const: ns1645057 - const: ns1655058 - const: ns16550a59 - const: ns1685060 - const: aspeed,ast2400-vuart61 - const: aspeed,ast2500-vuart62 - const: intel,xscale-uart63 - const: mrvl,pxa-uart64 - const: nuvoton,wpcm450-uart65 - const: nuvoton,npcm750-uart66 - const: nvidia,tegra20-uart67 - const: nxp,lpc3220-uart68 - items:69 - enum:70 - exar,xr16l255271 - exar,xr16l255172 - exar,xr16l255073 - const: ns825074 - items:75 - enum:76 - altr,16550-FIFO3277 - altr,16550-FIFO6478 - altr,16550-FIFO12879 - fsl,16550-FIFO6480 - fsl,ns1655081 - andestech,uart1655082 - nxp,lpc1850-uart83 - opencores,uart16550-rtlsvn10584 - ti,da830-uart85 - const: ns16550a86 - items:87 - enum:88 - ns1675089 - cavium,octeon-3860-uart90 - xlnx,xps-uart16550-2.00.b91 - ralink,rt2880-uart92 - enum:93 - ns16550 # Deprecated, unless the FIFO really is broken94 - ns16550a95 - items:96 - enum:97 - nuvoton,npcm845-uart98 - const: nuvoton,npcm750-uart99 - items:100 - enum:101 - ralink,mt7620a-uart102 - ralink,rt3052-uart103 - ralink,rt3883-uart104 - const: ralink,rt2880-uart105 - enum:106 - ns16550 # Deprecated, unless the FIFO really is broken107 - ns16550a108 - items:109 - enum:110 - mediatek,mt7622-btif111 - mediatek,mt7623-btif112 - const: mediatek,mtk-btif113 - items:114 - const: mrvl,mmp-uart115 - const: intel,xscale-uart116 - items:117 - enum:118 - nvidia,tegra30-uart119 - nvidia,tegra114-uart120 - nvidia,tegra124-uart121 - nvidia,tegra210-uart122 - nvidia,tegra186-uart123 - nvidia,tegra194-uart124 - nvidia,tegra234-uart125 - const: nvidia,tegra20-uart126 127 reg:128 maxItems: 1129 130 interrupts:131 maxItems: 1132 133 clock-frequency: true134 135 clocks:136 maxItems: 1137 138 resets:139 maxItems: 1140 141 current-speed:142 $ref: /schemas/types.yaml#/definitions/uint32143 description: The current active speed of the UART.144 145 reg-offset:146 $ref: /schemas/types.yaml#/definitions/uint32147 description: |148 Offset to apply to the mapbase from the start of the registers.149 150 reg-shift:151 description: Quantity to shift the register offsets by.152 153 reg-io-width:154 description: |155 The size (in bytes) of the IO accesses that should be performed on the156 device. There are some systems that require 32-bit accesses to the157 UART (e.g. TI davinci).158 159 used-by-rtas:160 type: boolean161 description: |162 Set to indicate that the port is in use by the OpenFirmware RTAS and163 should not be registered.164 165 no-loopback-test:166 type: boolean167 description: |168 Set to indicate that the port does not implement loopback test mode.169 170 fifo-size:171 $ref: /schemas/types.yaml#/definitions/uint32172 description: The fifo size of the UART.173 174 auto-flow-control:175 type: boolean176 description: |177 One way to enable automatic flow control support. The driver is178 allowed to detect support for the capability even without this179 property.180 181 tx-threshold:182 description: |183 Specify the TX FIFO low water indication for parts with programmable184 TX FIFO thresholds.185 186 overrun-throttle-ms:187 description: |188 How long to pause uart rx when input overrun is encountered.189 190 rts-gpios: true191 cts-gpios: true192 dtr-gpios: true193 dsr-gpios: true194 rng-gpios: true195 dcd-gpios: true196 197 aspeed,sirq-polarity-sense:198 $ref: /schemas/types.yaml#/definitions/phandle-array199 description: |200 Phandle to aspeed,ast2500-scu compatible syscon alongside register201 offset and bit number to identify how the SIRQ polarity should be202 configured. One possible data source is the LPC/eSPI mode bit. Only203 applicable to aspeed,ast2500-vuart.204 deprecated: true205 206 aspeed,lpc-io-reg:207 $ref: /schemas/types.yaml#/definitions/uint32-array208 maxItems: 1209 description: |210 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.211 212 aspeed,lpc-interrupts:213 $ref: /schemas/types.yaml#/definitions/uint32-array214 minItems: 2215 maxItems: 2216 description: |217 A 2-cell property describing the VUART SIRQ number and SIRQ218 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only219 applicable to aspeed,ast2500-vuart.220 221required:222 - reg223 - interrupts224 225unevaluatedProperties: false226 227examples:228 - |229 serial@80230000 {230 compatible = "ns8250";231 reg = <0x80230000 0x100>;232 interrupts = <10>;233 reg-shift = <2>;234 clock-frequency = <48000000>;235 };236 - |237 #include <dt-bindings/gpio/gpio.h>238 serial@49042000 {239 compatible = "andestech,uart16550", "ns16550a";240 reg = <0x49042000 0x400>;241 interrupts = <80>;242 clock-frequency = <48000000>;243 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;244 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;245 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;246 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;247 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;248 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;249 };250 - |251 #include <dt-bindings/clock/aspeed-clock.h>252 #include <dt-bindings/interrupt-controller/irq.h>253 serial@1e787000 {254 compatible = "aspeed,ast2500-vuart";255 reg = <0x1e787000 0x40>;256 reg-shift = <2>;257 interrupts = <8>;258 clocks = <&syscon ASPEED_CLK_APB>;259 no-loopback-test;260 aspeed,lpc-io-reg = <0x3f8>;261 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;262 };263 264...265