82 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence UART Controller8 9maintainers:10 - Michal Simek <michal.simek@amd.com>11 12properties:13 compatible:14 oneOf:15 - description: UART controller for Zynq-7xxx SoC16 items:17 - const: xlnx,xuartps18 - const: cdns,uart-r1p819 - description: UART controller for Zynq Ultrascale+ MPSoC20 items:21 - const: xlnx,zynqmp-uart22 - const: cdns,uart-r1p1223 24 reg:25 maxItems: 126 27 interrupts:28 maxItems: 129 30 clocks:31 maxItems: 232 33 clock-names:34 items:35 - const: uart_clk36 - const: pclk37 38 cts-override:39 description: |40 Override the CTS modem status signal. This signal will41 always be reported as active instead of being obtained42 from the modem status register. Define this if your serial43 port does not use this pin.44 type: boolean45 46 power-domains:47 maxItems: 148 49 resets:50 maxItems: 151 52required:53 - compatible54 - reg55 - interrupts56 - clocks57 - clock-names58 59allOf:60 - $ref: serial.yaml#61 - $ref: rs485.yaml#62 - if:63 properties:64 compatible:65 contains:66 const: cdns,uart-r1p867 then:68 properties:69 power-domains: false70 71unevaluatedProperties: false72 73examples:74 - |75 uart0: serial@e0000000 {76 compatible = "xlnx,xuartps", "cdns,uart-r1p8";77 clocks = <&clkc 23>, <&clkc 40>;78 clock-names = "uart_clk", "pclk";79 reg = <0xe0000000 0x1000>;80 interrupts = <0 27 4>;81 };82