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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)8 9maintainers:10 - Fabio Estevam <festevam@gmail.com>11 12properties:13 compatible:14 oneOf:15 - const: fsl,imx1-uart16 - const: fsl,imx21-uart17 - items:18 - enum:19 - fsl,imx25-uart20 - fsl,imx27-uart21 - fsl,imx31-uart22 - fsl,imx35-uart23 - fsl,imx50-uart24 - fsl,imx51-uart25 - fsl,imx53-uart26 - fsl,imx6q-uart27 - const: fsl,imx21-uart28 - items:29 - enum:30 - fsl,imx6sl-uart31 - fsl,imx6sll-uart32 - fsl,imx6sx-uart33 - const: fsl,imx6q-uart34 - const: fsl,imx21-uart35 - items:36 - enum:37 - fsl,imx6ul-uart38 - fsl,imx7d-uart39 - fsl,imx8mm-uart40 - fsl,imx8mn-uart41 - fsl,imx8mp-uart42 - fsl,imx8mq-uart43 - const: fsl,imx6q-uart44 45 reg:46 maxItems: 147 48 clocks:49 maxItems: 250 51 clock-names:52 items:53 - const: ipg54 - const: per55 56 dmas:57 items:58 - description: DMA controller phandle and request line for RX59 - description: DMA controller phandle and request line for TX60 61 dma-names:62 items:63 - const: rx64 - const: tx65 66 interrupts:67 items:68 - description: UART RX Interrupt69 - description: UART TX Interrupt70 - description: UART RTS Interrupt71 minItems: 172 73 wakeup-source: true74 75 fsl,dte-mode:76 $ref: /schemas/types.yaml#/definitions/flag77 description: |78 Indicate the uart works in DTE mode. The uart works in DCE mode by default.79 80 fsl,inverted-tx:81 $ref: /schemas/types.yaml#/definitions/flag82 description: |83 Indicate that the hardware attached to the peripheral inverts the signal84 transmitted, and that the peripheral should invert its output using the85 INVT registers.86 87 fsl,inverted-rx:88 $ref: /schemas/types.yaml#/definitions/flag89 description: |90 Indicate that the hardware attached to the peripheral inverts the signal91 received, and that the peripheral should invert its input using the92 INVR registers.93 94 fsl,dma-info:95 $ref: /schemas/types.yaml#/definitions/uint32-array96 minItems: 297 maxItems: 298 description: |99 First cell contains the size of DMA buffer chunks, second cell contains100 the amount of chunks used for the device. Multiplying both numbers is101 the total size of memory used for receiving data.102 When not being configured the system will use default settings, which103 are sensible for most use cases. If you need low latency processing on104 slow connections this needs to be configured appropriately.105 106required:107 - compatible108 - reg109 - clocks110 - clock-names111 - interrupts112 113allOf:114 - $ref: serial.yaml#115 - $ref: rs485.yaml#116 117 - if:118 properties:119 compatible:120 contains:121 const: fsl,imx1-uart122 then:123 properties:124 interrupts:125 minItems: 3126 maxItems: 3127 else:128 properties:129 interrupts:130 maxItems: 1131 132unevaluatedProperties: false133 134examples:135 - |136 #include <dt-bindings/clock/imx5-clock.h>137 138 aliases {139 serial0 = &uart1;140 };141 142 uart1: serial@73fbc000 {143 compatible = "fsl,imx51-uart", "fsl,imx21-uart";144 reg = <0x73fbc000 0x4000>;145 interrupts = <31>;146 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,147 <&clks IMX5_CLK_UART1_PER_GATE>;148 clock-names = "ipg", "per";149 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;150 dma-names = "rx", "tx";151 uart-has-rtscts;152 fsl,dte-mode;153 };154