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1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm MSM Serial UARTDM8 9maintainers:10 - Andy Gross <agross@kernel.org>11 - Bjorn Andersson <bjorn.andersson@linaro.org>12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>13 14description: |15 The MSM serial UARTDM hardware is designed for high-speed use cases where the16 transmit and/or receive channels can be offloaded to a dma-engine. From a17 software perspective it's mostly compatible with the MSM serial UART except18 that it supports reading and writing multiple characters at a time.19 20 Note:: Aliases may be defined to ensure the correct ordering of the UARTs.21 The alias serialN will result in the UART being assigned port N. If any22 serialN alias exists, then an alias must exist for each enabled UART. The23 serialN aliases should be in a .dts file instead of in a .dtsi file.24 25properties:26 compatible:27 items:28 - enum:29 - qcom,msm-uartdm-v1.130 - qcom,msm-uartdm-v1.231 - qcom,msm-uartdm-v1.332 - qcom,msm-uartdm-v1.433 - const: qcom,msm-uartdm34 35 clocks:36 maxItems: 237 38 clock-names:39 items:40 - const: core41 - const: iface42 43 dmas:44 maxItems: 245 46 dma-names:47 items:48 - const: tx49 - const: rx50 51 interconnects:52 maxItems: 153 54 interrupts:55 maxItems: 156 57 operating-points-v2: true58 59 power-domains:60 maxItems: 161 62 qcom,rx-crci:63 $ref: /schemas/types.yaml#/definitions/uint3264 description:65 Identificator for Client Rate Control Interface to be used with RX DMA66 channel. Required when using DMA for reception with UARTDM v1.3 and67 below.68 69 qcom,tx-crci:70 $ref: /schemas/types.yaml#/definitions/uint3271 description:72 Identificator for Client Rate Control Interface to be used with TX DMA73 channel. Required when using DMA for transmission with UARTDM v1.3 and74 below.75 76 reg:77 minItems: 178 items:79 - description: Main control registers80 - description: An optional second register location shall specify the GSBI control region.81 82required:83 - compatible84 - clock-names85 - clocks86 - interrupts87 - reg88 89allOf:90 - $ref: /schemas/serial/serial.yaml#91 92 - if:93 properties:94 compatible:95 contains:96 const: qcom,msm-uartdm-v1.397 then:98 properties:99 reg:100 minItems: 2101 else:102 properties:103 reg:104 maxItems: 1105 106unevaluatedProperties: false107 108examples:109 - |110 #include <dt-bindings/interconnect/qcom,msm8996.h>111 #include <dt-bindings/interrupt-controller/arm-gic.h>112 #include <dt-bindings/power/qcom-rpmpd.h>113 114 serial@f991e000 {115 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";116 reg = <0xf991e000 0x1000>;117 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;118 clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;119 clock-names = "core", "iface";120 dmas = <&dma0 0>, <&dma0 1>;121 dma-names = "tx", "rx";122 power-domains = <&rpmpd MSM8996_VDDCX>;123 operating-points-v2 = <&uart_opp_table>;124 interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;125 };126