152 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/serial/renesas,hscif.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF)8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 12allOf:13 - $ref: serial.yaml#14 15properties:16 compatible:17 oneOf:18 - items:19 - enum:20 - renesas,hscif-r8a7778 # R-Car M121 - renesas,hscif-r8a7779 # R-Car H122 - const: renesas,rcar-gen1-hscif # R-Car Gen123 - const: renesas,hscif # generic HSCIF compatible UART24 25 - items:26 - enum:27 - renesas,hscif-r8a7742 # RZ/G1H28 - renesas,hscif-r8a7743 # RZ/G1M29 - renesas,hscif-r8a7744 # RZ/G1N30 - renesas,hscif-r8a7745 # RZ/G1E31 - renesas,hscif-r8a77470 # RZ/G1C32 - renesas,hscif-r8a7790 # R-Car H233 - renesas,hscif-r8a7791 # R-Car M2-W34 - renesas,hscif-r8a7792 # R-Car V2H35 - renesas,hscif-r8a7793 # R-Car M2-N36 - renesas,hscif-r8a7794 # R-Car E237 - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G138 - const: renesas,hscif # generic HSCIF compatible UART39 40 - items:41 - enum:42 - renesas,hscif-r8a774a1 # RZ/G2M43 - renesas,hscif-r8a774b1 # RZ/G2N44 - renesas,hscif-r8a774c0 # RZ/G2E45 - renesas,hscif-r8a774e1 # RZ/G2H46 - renesas,hscif-r8a7795 # R-Car H347 - renesas,hscif-r8a7796 # R-Car M3-W48 - renesas,hscif-r8a77961 # R-Car M3-W+49 - renesas,hscif-r8a77965 # R-Car M3-N50 - renesas,hscif-r8a77970 # R-Car V3M51 - renesas,hscif-r8a77980 # R-Car V3H52 - renesas,hscif-r8a77990 # R-Car E353 - renesas,hscif-r8a77995 # R-Car D354 - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G255 - const: renesas,hscif # generic HSCIF compatible UART56 57 - items:58 - enum:59 - renesas,hscif-r8a779a0 # R-Car V3U60 - renesas,hscif-r8a779f0 # R-Car S4-861 - renesas,hscif-r8a779g0 # R-Car V4H62 - renesas,hscif-r8a779h0 # R-Car V4M63 - const: renesas,rcar-gen4-hscif # R-Car Gen464 - const: renesas,hscif # generic HSCIF compatible UART65 66 reg:67 maxItems: 168 69 interrupts:70 maxItems: 171 72 clocks:73 minItems: 174 maxItems: 475 76 clock-names:77 minItems: 178 maxItems: 479 items:80 enum:81 - fck # UART functional clock82 - hsck # optional external clock input83 - brg_int # optional internal clock source for BRG frequency divider84 - scif_clk # optional external clock source for BRG frequency divider85 86 power-domains:87 maxItems: 188 89 resets:90 maxItems: 191 92 dmas:93 minItems: 294 maxItems: 495 description:96 Must contain a list of pairs of references to DMA specifiers, one for97 transmission, and one for reception.98 99 dma-names:100 minItems: 2101 maxItems: 4102 items:103 enum:104 - tx105 - rx106 107required:108 - compatible109 - reg110 - interrupts111 - clocks112 - clock-names113 - power-domains114 115if:116 properties:117 compatible:118 contains:119 enum:120 - renesas,rcar-gen2-hscif121 - renesas,rcar-gen3-hscif122 - renesas,rcar-gen4-hscif123then:124 required:125 - resets126 127unevaluatedProperties: false128 129examples:130 - |131 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>132 #include <dt-bindings/interrupt-controller/arm-gic.h>133 #include <dt-bindings/power/r8a7795-sysc.h>134 aliases {135 serial1 = &hscif1;136 };137 138 hscif1: serial@e6550000 {139 compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif",140 "renesas,hscif";141 reg = <0xe6550000 96>;142 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;143 clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,144 <&scif_clk>;145 clock-names = "fck", "brg_int", "scif_clk";146 dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>;147 dma-names = "tx", "rx", "tx", "rx";148 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;149 resets = <&cpg 519>;150 uart-has-rtscts;151 };152