110 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/serial/renesas,sci.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas Serial Communication Interface8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 12allOf:13 - $ref: serial.yaml#14 15properties:16 compatible:17 oneOf:18 - items:19 - enum:20 - renesas,r9a07g043-sci # RZ/G2UL and RZ/Five21 - renesas,r9a07g044-sci # RZ/G2{L,LC}22 - renesas,r9a07g054-sci # RZ/V2L23 - const: renesas,sci # generic SCI compatible UART24 25 - items:26 - const: renesas,sci # generic SCI compatible UART27 28 reg:29 maxItems: 130 31 interrupts:32 items:33 - description: Error interrupt34 - description: Receive buffer full interrupt35 - description: Transmit buffer empty interrupt36 - description: Transmit end interrupt37 38 interrupt-names:39 items:40 - const: eri41 - const: rxi42 - const: txi43 - const: tei44 45 clocks:46 minItems: 147 maxItems: 248 49 clock-names:50 minItems: 151 maxItems: 252 items:53 enum:54 - fck # UART functional clock55 - sck # optional external clock input56 57 uart-has-rtscts: false58 59required:60 - compatible61 - reg62 - interrupts63 - clocks64 - clock-names65 66if:67 properties:68 compatible:69 contains:70 enum:71 - renesas,r9a07g043-sci72 - renesas,r9a07g044-sci73 - renesas,r9a07g054-sci74then:75 properties:76 resets:77 maxItems: 178 79 power-domains:80 maxItems: 181 82 required:83 - resets84 - power-domains85 86unevaluatedProperties: false87 88examples:89 - |90 #include <dt-bindings/clock/r9a07g044-cpg.h>91 #include <dt-bindings/interrupt-controller/arm-gic.h>92 93 aliases {94 serial0 = &sci0;95 };96 97 sci0: serial@1004d000 {98 compatible = "renesas,r9a07g044-sci", "renesas,sci";99 reg = <0x1004d000 0x400>;100 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,101 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,102 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,103 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;104 interrupt-names = "eri", "rxi", "txi", "tei";105 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;106 clock-names = "fck";107 power-domains = <&cpg>;108 resets = <&cpg R9A07G044_SCI0_RST>;109 };110