272 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/serial/renesas,scif.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas Serial Communication Interface with FIFO (SCIF)8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 12properties:13 compatible:14 oneOf:15 - items:16 - enum:17 - renesas,scif-r7s72100 # RZ/A1H18 - const: renesas,scif # generic SCIF compatible UART19 20 - items:21 - enum:22 - renesas,scif-r7s9210 # RZ/A223 24 - items:25 - enum:26 - renesas,scif-r8a7778 # R-Car M127 - renesas,scif-r8a7779 # R-Car H128 - const: renesas,rcar-gen1-scif # R-Car Gen129 - const: renesas,scif # generic SCIF compatible UART30 31 - items:32 - enum:33 - renesas,scif-r8a7742 # RZ/G1H34 - renesas,scif-r8a7743 # RZ/G1M35 - renesas,scif-r8a7744 # RZ/G1N36 - renesas,scif-r8a7745 # RZ/G1E37 - renesas,scif-r8a77470 # RZ/G1C38 - renesas,scif-r8a7790 # R-Car H239 - renesas,scif-r8a7791 # R-Car M2-W40 - renesas,scif-r8a7792 # R-Car V2H41 - renesas,scif-r8a7793 # R-Car M2-N42 - renesas,scif-r8a7794 # R-Car E243 - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G144 - const: renesas,scif # generic SCIF compatible UART45 46 - items:47 - enum:48 - renesas,scif-r8a774a1 # RZ/G2M49 - renesas,scif-r8a774a3 # RZ/G2M v3.050 - renesas,scif-r8a774b1 # RZ/G2N51 - renesas,scif-r8a774c0 # RZ/G2E52 - renesas,scif-r8a774e1 # RZ/G2H53 - renesas,scif-r8a7795 # R-Car H354 - renesas,scif-r8a7796 # R-Car M3-W55 - renesas,scif-r8a77961 # R-Car M3-W+56 - renesas,scif-r8a77965 # R-Car M3-N57 - renesas,scif-r8a77970 # R-Car V3M58 - renesas,scif-r8a77980 # R-Car V3H59 - renesas,scif-r8a77990 # R-Car E360 - renesas,scif-r8a77995 # R-Car D361 - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G262 - const: renesas,scif # generic SCIF compatible UART63 64 - items:65 - enum:66 - renesas,scif-r8a779a0 # R-Car V3U67 - renesas,scif-r8a779f0 # R-Car S4-868 - renesas,scif-r8a779g0 # R-Car V4H69 - renesas,scif-r8a779h0 # R-Car V4M70 - const: renesas,rcar-gen4-scif # R-Car Gen471 - const: renesas,scif # generic SCIF compatible UART72 73 - items:74 - enum:75 - renesas,scif-r9a07g044 # RZ/G2{L,LC}76 77 - items:78 - enum:79 - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five80 - renesas,scif-r9a07g054 # RZ/V2L81 - renesas,scif-r9a08g045 # RZ/G3S82 - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback83 84 - const: renesas,scif-r9a09g057 # RZ/V2H(P)85 86 reg:87 maxItems: 188 89 interrupts:90 oneOf:91 - items:92 - description: A combined interrupt93 - items:94 - description: Error interrupt95 - description: Receive buffer full interrupt96 - description: Transmit buffer empty interrupt97 - description: Break interrupt98 - description: Data Ready interrupt99 - description: Transmit End interrupt100 - description: Transmit End/Data Ready interrupt101 - description: Receive buffer full interrupt (EDGE trigger)102 - description: Transmit buffer empty interrupt (EDGE trigger)103 minItems: 4104 105 interrupt-names:106 minItems: 4107 items:108 - const: eri109 - const: rxi110 - const: txi111 - const: bri112 - const: dri113 - const: tei114 - const: tei-dri115 - const: rxi-edge116 - const: txi-edge117 118 clocks:119 minItems: 1120 maxItems: 4121 122 clock-names:123 minItems: 1124 maxItems: 4125 items:126 enum:127 - fck # UART functional clock128 - sck # optional external clock input129 - brg_int # optional internal clock source for BRG frequency divider130 - scif_clk # optional external clock source for BRG frequency divider131 132 power-domains:133 maxItems: 1134 135 resets:136 maxItems: 1137 138 dmas:139 minItems: 2140 maxItems: 4141 description:142 Must contain a list of pairs of references to DMA specifiers, one for143 transmission, and one for reception.144 145 dma-names:146 minItems: 2147 maxItems: 4148 items:149 enum:150 - tx151 - rx152 153required:154 - compatible155 - reg156 - interrupts157 - clocks158 - clock-names159 - power-domains160 161allOf:162 - $ref: serial.yaml#163 164 - if:165 properties:166 compatible:167 contains:168 enum:169 - renesas,rcar-gen2-scif170 - renesas,rcar-gen3-scif171 - renesas,rcar-gen4-scif172 - renesas,scif-r9a07g044173 - renesas,scif-r9a09g057174 then:175 required:176 - resets177 178 - if:179 properties:180 compatible:181 contains:182 enum:183 - renesas,rcar-gen1-scif184 - renesas,rcar-gen2-scif185 - renesas,rcar-gen3-scif186 - renesas,rcar-gen4-scif187 then:188 properties:189 interrupts:190 maxItems: 1191 192 interrupt-names: false193 else:194 required:195 - interrupt-names196 197 - if:198 properties:199 compatible:200 contains:201 enum:202 - renesas,scif-r7s72100203 then:204 properties:205 interrupts:206 minItems: 4207 maxItems: 4208 209 interrupt-names:210 maxItems: 4211 212 - if:213 properties:214 compatible:215 contains:216 enum:217 - renesas,scif-r7s9210218 - renesas,scif-r9a07g044219 then:220 properties:221 interrupts:222 minItems: 6223 maxItems: 6224 225 interrupt-names:226 minItems: 6227 maxItems: 6228 229 - if:230 properties:231 compatible:232 contains:233 const: renesas,scif-r9a09g057234 then:235 properties:236 clocks:237 maxItems: 1238 239 clock-names:240 maxItems: 1241 242 interrupts:243 minItems: 9244 245 interrupt-names:246 minItems: 9247 248unevaluatedProperties: false249 250examples:251 - |252 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>253 #include <dt-bindings/interrupt-controller/arm-gic.h>254 #include <dt-bindings/power/r8a7791-sysc.h>255 aliases {256 serial0 = &scif0;257 };258 259 scif0: serial@e6e60000 {260 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",261 "renesas,scif";262 reg = <0xe6e60000 64>;263 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;264 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,265 <&scif_clk>;266 clock-names = "fck", "brg_int", "scif_clk";267 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;268 dma-names = "tx", "rx", "tx", "rx";269 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;270 resets = <&cpg 721>;271 };272