206 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: PowerQUICC CPM Time-slot assigner (TSA) controller8 9maintainers:10 - Herve Codina <herve.codina@bootlin.com>11 12description:13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.14 Its purpose is to route some TDM time-slots to other internal serial15 controllers.16 17properties:18 compatible:19 items:20 - enum:21 - fsl,mpc885-tsa22 - fsl,mpc866-tsa23 - const: fsl,cpm1-tsa24 25 reg:26 items:27 - description: SI (Serial Interface) register base28 - description: SI RAM base29 30 reg-names:31 items:32 - const: si_regs33 - const: si_ram34 35 '#address-cells':36 const: 137 38 '#size-cells':39 const: 040 41patternProperties:42 '^tdm@[0-1]$':43 description:44 The TDM managed by this controller45 type: object46 47 additionalProperties: false48 49 properties:50 reg:51 minimum: 052 maximum: 153 description:54 The TDM number for this TDM, 0 for TDMa and 1 for TDMb55 56 fsl,common-rxtx-pins:57 $ref: /schemas/types.yaml#/definitions/flag58 description:59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.61 Without the 'fsl,common-rxtx-pins' property, the four pins are used.62 With the 'fsl,common-rxtx-pins' property, two pins are used.63 64 clocks:65 minItems: 266 items:67 - description: External clock connected to L1RSYNC pin68 - description: External clock connected to L1RCLK pin69 - description: External clock connected to L1TSYNC pin70 - description: External clock connected to L1TCLK pin71 72 clock-names:73 minItems: 274 items:75 - const: l1rsync76 - const: l1rclk77 - const: l1tsync78 - const: l1tclk79 80 fsl,rx-frame-sync-delay-bits:81 enum: [0, 1, 2, 3]82 default: 083 description: |84 Receive frame sync delay in number of bits.85 Indicates the delay between the Rx sync and the first bit of the Rx86 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.87 88 fsl,tx-frame-sync-delay-bits:89 enum: [0, 1, 2, 3]90 default: 091 description: |92 Transmit frame sync delay in number of bits.93 Indicates the delay between the Tx sync and the first bit of the Tx94 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.95 96 fsl,clock-falling-edge:97 $ref: /schemas/types.yaml#/definitions/flag98 description:99 Data is sent on falling edge of the clock (and received on the rising100 edge). If 'clock-falling-edge' is not present, data is sent on the101 rising edge (and received on the falling edge).102 103 fsl,fsync-rising-edge:104 $ref: /schemas/types.yaml#/definitions/flag105 description:106 Frame sync pulses are sampled with the rising edge of the channel107 clock. If 'fsync-rising-edge' is not present, pulses are sampled with108 the falling edge.109 110 fsl,double-speed-clock:111 $ref: /schemas/types.yaml#/definitions/flag112 description:113 The channel clock is twice the data rate.114 115 patternProperties:116 '^fsl,[rt]x-ts-routes$':117 $ref: /schemas/types.yaml#/definitions/uint32-matrix118 description: |119 A list of tuple that indicates the Tx or Rx time-slots routes.120 items:121 items:122 - description:123 The number of time-slots124 minimum: 1125 maximum: 64126 - description: |127 The source (Tx) or destination (Rx) serial interface128 (dt-bindings/soc/cpm1-fsl,tsa.h defines these values)129 - 0: No destination130 - 1: SCC2131 - 2: SCC3132 - 3: SCC4133 - 4: SMC1134 - 5: SMC2135 enum: [0, 1, 2, 3, 4, 5]136 minItems: 1137 maxItems: 64138 139 allOf:140 # If fsl,common-rxtx-pins is present, only 2 clocks are needed.141 # Else, the 4 clocks must be present.142 - if:143 required:144 - fsl,common-rxtx-pins145 then:146 properties:147 clocks:148 maxItems: 2149 clock-names:150 maxItems: 2151 else:152 properties:153 clocks:154 minItems: 4155 clock-names:156 minItems: 4157 158 required:159 - reg160 - clocks161 - clock-names162 163required:164 - compatible165 - reg166 - reg-names167 - '#address-cells'168 - '#size-cells'169 170additionalProperties: false171 172examples:173 - |174 #include <dt-bindings/soc/cpm1-fsl,tsa.h>175 176 tsa@ae0 {177 compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";178 reg = <0xae0 0x10>,179 <0xc00 0x200>;180 reg-names = "si_regs", "si_ram";181 182 #address-cells = <1>;183 #size-cells = <0>;184 185 tdm@0 {186 /* TDMa */187 reg = <0>;188 189 clocks = <&clk_l1rsynca>, <&clk_l1rclka>;190 clock-names = "l1rsync", "l1rclk";191 192 fsl,common-rxtx-pins;193 fsl,fsync-rising-edge;194 195 fsl,tx-ts-routes = <2 0>, /* TS 0..1 */196 <24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */197 <1 0>, /* TS 26 */198 <5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */199 200 fsl,rx-ts-routes = <2 0>, /* TS 0..1 */201 <24 FSL_CPM_TSA_SCC4>, /* 2..25 */202 <1 0>, /* TS 26 */203 <5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */204 };205 };206