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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: PowerQUICC QE Time-slot assigner (TSA) controller8 9maintainers:10 - Herve Codina <herve.codina@bootlin.com>11 12description:13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.14 Its purpose is to route some TDM time-slots to other internal serial15 controllers.16 17properties:18 compatible:19 items:20 - enum:21 - fsl,mpc8321-tsa22 - const: fsl,qe-tsa23 24 reg:25 items:26 - description: SI (Serial Interface) register base27 - description: SI RAM base28 29 reg-names:30 items:31 - const: si_regs32 - const: si_ram33 34 '#address-cells':35 const: 136 37 '#size-cells':38 const: 039 40patternProperties:41 '^tdm@[0-3]$':42 description:43 The TDM managed by this controller44 type: object45 46 additionalProperties: false47 48 properties:49 reg:50 minimum: 051 maximum: 352 description:53 The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 354 for TDMd.55 56 fsl,common-rxtx-pins:57 $ref: /schemas/types.yaml#/definitions/flag58 description:59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.61 Without the 'fsl,common-rxtx-pins' property, the four pins are used.62 With the 'fsl,common-rxtx-pins' property, two pins are used.63 64 clocks:65 minItems: 266 items:67 - description: Receive sync clock68 - description: Receive data clock69 - description: Transmit sync clock70 - description: Transmit data clock71 72 clock-names:73 minItems: 274 items:75 - const: rsync76 - const: rclk77 - const: tsync78 - const: tclk79 80 fsl,rx-frame-sync-delay-bits:81 enum: [0, 1, 2, 3]82 default: 083 description: |84 Receive frame sync delay in number of bits.85 Indicates the delay between the Rx sync and the first bit of the Rx86 frame.87 88 fsl,tx-frame-sync-delay-bits:89 enum: [0, 1, 2, 3]90 default: 091 description: |92 Transmit frame sync delay in number of bits.93 Indicates the delay between the Tx sync and the first bit of the Tx94 frame.95 96 fsl,clock-falling-edge:97 $ref: /schemas/types.yaml#/definitions/flag98 description:99 Data is sent on falling edge of the clock (and received on the rising100 edge). If not present, data is sent on the rising edge (and received101 on the falling edge).102 103 fsl,fsync-rising-edge:104 $ref: /schemas/types.yaml#/definitions/flag105 description:106 Frame sync pulses are sampled with the rising edge of the channel107 clock. If not present, pulses are sampled with the falling edge.108 109 fsl,fsync-active-low:110 $ref: /schemas/types.yaml#/definitions/flag111 description:112 Frame sync signals are active on low logic level.113 If not present, sync signals are active on high level.114 115 fsl,double-speed-clock:116 $ref: /schemas/types.yaml#/definitions/flag117 description:118 The channel clock is twice the data rate.119 120 patternProperties:121 '^fsl,[rt]x-ts-routes$':122 $ref: /schemas/types.yaml#/definitions/uint32-matrix123 description: |124 A list of tuple that indicates the Tx or Rx time-slots routes.125 items:126 items:127 - description:128 The number of time-slots129 minimum: 1130 maximum: 64131 - description: |132 The source (Tx) or destination (Rx) serial interface133 (dt-bindings/soc/qe-fsl,tsa.h defines these values)134 - 0: No destination135 - 1: UCC1136 - 2: UCC2137 - 3: UCC3138 - 4: UCC4139 - 5: UCC5140 enum: [0, 1, 2, 3, 4, 5]141 minItems: 1142 maxItems: 64143 144 allOf:145 # If fsl,common-rxtx-pins is present, only 2 clocks are needed.146 # Else, the 4 clocks must be present.147 - if:148 required:149 - fsl,common-rxtx-pins150 then:151 properties:152 clocks:153 maxItems: 2154 clock-names:155 maxItems: 2156 else:157 properties:158 clocks:159 minItems: 4160 clock-names:161 minItems: 4162 163 required:164 - reg165 - clocks166 - clock-names167 168required:169 - compatible170 - reg171 - reg-names172 - '#address-cells'173 - '#size-cells'174 175additionalProperties: false176 177examples:178 - |179 #include <dt-bindings/soc/qe-fsl,tsa.h>180 181 tsa@ae0 {182 compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa";183 reg = <0xae0 0x10>,184 <0xc00 0x200>;185 reg-names = "si_regs", "si_ram";186 187 #address-cells = <1>;188 #size-cells = <0>;189 190 tdm@0 {191 /* TDMa */192 reg = <0>;193 194 clocks = <&clk_l1rsynca>, <&clk_l1rclka>;195 clock-names = "rsync", "rclk";196 197 fsl,common-rxtx-pins;198 fsl,fsync-rising-edge;199 200 fsl,tx-ts-routes = <2 0>, /* TS 0..1 */201 <24 FSL_QE_TSA_UCC4>, /* TS 2..25 */202 <1 0>, /* TS 26 */203 <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */204 205 fsl,rx-ts-routes = <2 0>, /* TS 0..1 */206 <24 FSL_QE_TSA_UCC4>, /* 2..25 */207 <1 0>, /* TS 26 */208 <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */209 };210 };211