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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: PowerQUICC QE QUICC Multichannel Controller (QMC)8 9maintainers:10 - Herve Codina <herve.codina@bootlin.com>11 12description:13 The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one14 serial controller using the same TDM physical interface routed from TSA.15 16properties:17 compatible:18 items:19 - enum:20 - fsl,mpc8321-ucc-qmc21 - const: fsl,qe-ucc-qmc22 23 reg:24 items:25 - description: UCC (Unified communication controller) register base26 - description: Dual port ram base27 28 reg-names:29 items:30 - const: ucc_regs31 - const: dpram32 33 interrupts:34 maxItems: 135 description: UCC interrupt line in the QE interrupt controller36 37 fsl,tsa-serial:38 $ref: /schemas/types.yaml#/definitions/phandle-array39 items:40 - items:41 - description: phandle to TSA node42 - enum: [1, 2, 3, 4, 5]43 description: |44 TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these45 values)46 - 1: UCC147 - 2: UCC248 - 3: UCC349 - 4: UCC450 - 5: UCC551 description:52 Should be a phandle/number pair. The phandle to TSA node and the TSA53 serial interface to use.54 55 fsl,soft-qmc:56 $ref: /schemas/types.yaml#/definitions/string57 description:58 Soft QMC firmware name to load. If this property is omitted, no firmware59 are used.60 61 '#address-cells':62 const: 163 64 '#size-cells':65 const: 066 67patternProperties:68 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':69 description:70 A channel managed by this controller71 type: object72 additionalProperties: false73 74 properties:75 compatible:76 items:77 - enum:78 - fsl,mpc8321-ucc-qmc-hdlc79 - const: fsl,qe-ucc-qmc-hdlc80 - const: fsl,qmc-hdlc81 82 reg:83 minimum: 084 maximum: 6385 description:86 The channel number87 88 fsl,operational-mode:89 $ref: /schemas/types.yaml#/definitions/string90 enum: [transparent, hdlc]91 default: transparent92 description: |93 The channel operational mode94 - hdlc: The channel handles HDLC frames95 - transparent: The channel handles raw data without any processing96 97 fsl,reverse-data:98 $ref: /schemas/types.yaml#/definitions/flag99 description:100 The bit order as seen on the channels is reversed,101 transmitting/receiving the MSB of each octet first.102 This flag is used only in 'transparent' mode.103 104 fsl,tx-ts-mask:105 $ref: /schemas/types.yaml#/definitions/uint64106 description:107 Channel assigned Tx time-slots within the Tx time-slots routed by the108 TSA to this cell.109 110 fsl,rx-ts-mask:111 $ref: /schemas/types.yaml#/definitions/uint64112 description:113 Channel assigned Rx time-slots within the Rx time-slots routed by the114 TSA to this cell.115 116 fsl,framer:117 $ref: /schemas/types.yaml#/definitions/phandle118 description:119 phandle to the framer node. The framer is in charge of an E1/T1 line120 interface connected to the TDM bus. It can be used to get the E1/T1 line121 status such as link up/down.122 123 allOf:124 - if:125 properties:126 compatible:127 not:128 contains:129 const: fsl,qmc-hdlc130 then:131 properties:132 fsl,framer: false133 134 required:135 - reg136 - fsl,tx-ts-mask137 - fsl,rx-ts-mask138 139required:140 - compatible141 - reg142 - reg-names143 - interrupts144 - fsl,tsa-serial145 - '#address-cells'146 - '#size-cells'147 148additionalProperties: false149 150examples:151 - |152 #include <dt-bindings/soc/qe-fsl,tsa.h>153 154 qmc@a60 {155 compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";156 reg = <0x3200 0x200>,157 <0x10000 0x1000>;158 reg-names = "ucc_regs", "dpram";159 interrupts = <35>;160 interrupt-parent = <&qeic>;161 fsl,soft-qmc = "fsl_qe_ucode_qmc_8321_11.bin";162 163 #address-cells = <1>;164 #size-cells = <0>;165 166 fsl,tsa-serial = <&tsa FSL_QE_TSA_UCC4>;167 168 channel@16 {169 /* Ch16 : First 4 even TS from all routed from TSA */170 reg = <16>;171 fsl,operational-mode = "transparent";172 fsl,reverse-data;173 fsl,tx-ts-mask = <0x00000000 0x000000aa>;174 fsl,rx-ts-mask = <0x00000000 0x000000aa>;175 };176 177 channel@17 {178 /* Ch17 : First 4 odd TS from all routed from TSA */179 reg = <17>;180 fsl,operational-mode = "transparent";181 fsl,reverse-data;182 fsl,tx-ts-mask = <0x00000000 0x00000055>;183 fsl,rx-ts-mask = <0x00000000 0x00000055>;184 };185 186 channel@19 {187 /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */188 compatible = "fsl,mpc8321-ucc-qmc-hdlc",189 "fsl,qe-ucc-qmc-hdlc",190 "fsl,qmc-hdlc";191 reg = <19>;192 fsl,operational-mode = "hdlc";193 fsl,tx-ts-mask = <0x00000000 0x0000ff00>;194 fsl,rx-ts-mask = <0x00000000 0x0000ff00>;195 fsl,framer = <&framer>;196 };197 };198