141 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: High-Level Data Link Control(HDLC)8 9description: HDLC part in Universal communication controllers (UCCs)10 11maintainers:12 - Frank Li <Frank.Li@nxp.com>13 14properties:15 compatible:16 const: fsl,ucc-hdlc17 18 reg:19 maxItems: 120 21 interrupts:22 maxItems: 123 24 cell-index:25 $ref: /schemas/types.yaml#/definitions/uint3226 27 rx-clock-name:28 $ref: /schemas/types.yaml#/definitions/string29 oneOf:30 - pattern: "^brg([0-9]|1[0-6])$"31 - pattern: "^clk([0-9]|1[0-9]|2[0-4])$"32 33 tx-clock-name:34 $ref: /schemas/types.yaml#/definitions/string35 oneOf:36 - pattern: "^brg([0-9]|1[0-6])$"37 - pattern: "^clk([0-9]|1[0-9]|2[0-4])$"38 39 fsl,tdm-interface:40 $ref: /schemas/types.yaml#/definitions/flag41 description: Specify that hdlc is based on tdm-interface42 43 fsl,rx-sync-clock:44 $ref: /schemas/types.yaml#/definitions/string45 description: rx-sync46 enum:47 - none48 - rsync_pin49 - brg950 - brg1051 - brg1152 - brg1353 - brg1454 - brg1555 56 fsl,tx-sync-clock:57 $ref: /schemas/types.yaml#/definitions/string58 description: tx-sync59 enum:60 - none61 - tsync_pin62 - brg963 - brg1064 - brg1165 - brg1366 - brg1467 - brg1568 69 fsl,tdm-framer-type:70 $ref: /schemas/types.yaml#/definitions/string71 description: required for tdm interface72 enum: [e1, t1]73 74 fsl,tdm-id:75 $ref: /schemas/types.yaml#/definitions/uint3276 description: number of TDM ID77 78 fsl,tx-timeslot-mask:79 $ref: /schemas/types.yaml#/definitions/uint3280 description:81 required for tdm interface.82 time slot mask for TDM operation. Indicates which time83 slots used for transmitting and receiving.84 85 fsl,rx-timeslot-mask:86 $ref: /schemas/types.yaml#/definitions/uint3287 description:88 required for tdm interface.89 time slot mask for TDM operation. Indicates which time90 slots used for transmitting and receiving.91 92 fsl,siram-entry-id:93 $ref: /schemas/types.yaml#/definitions/uint3294 description:95 required for tdm interface96 Must be 0,2,4...64. the number of TDM entry.97 98 fsl,tdm-internal-loopback:99 $ref: /schemas/types.yaml#/definitions/flag100 description:101 optional for tdm interface102 Internal loopback connecting on TDM layer.103 104 fsl,hmask:105 $ref: /schemas/types.yaml#/definitions/uint16106 description: |107 HDLC address recognition. Set to zero to disable108 address filtering of packets:109 fsl,hmask = /bits/ 16 <0x0000>;110 111required:112 - compatible113 - reg114 115additionalProperties: false116 117examples:118 - |119 communication@2000 {120 compatible = "fsl,ucc-hdlc";121 reg = <0x2000 0x200>;122 rx-clock-name = "clk8";123 tx-clock-name = "clk9";124 fsl,rx-sync-clock = "rsync_pin";125 fsl,tx-sync-clock = "tsync_pin";126 fsl,tx-timeslot-mask = <0xfffffffe>;127 fsl,rx-timeslot-mask = <0xfffffffe>;128 fsl,tdm-framer-type = "e1";129 fsl,tdm-id = <0>;130 fsl,siram-entry-id = <0>;131 fsl,tdm-interface;132 };133 134 - |135 communication@2000 {136 compatible = "fsl,ucc-hdlc";137 reg = <0x2000 0x200>;138 rx-clock-name = "brg1";139 tx-clock-name = "brg1";140 };141