brintos

brintos / linux-shallow public Read only

0
0
Text · 1.8 KiB · 4380b98 Raw
69 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek color correction8 9maintainers:10  - Matthias Brugger <matthias.bgg@gmail.com>11  - Moudy Ho <moudy.ho@mediatek.com>12 13description: |14  MediaTek color correction with 3X3 matrix.15 16properties:17  compatible:18    items:19      - enum:20          - mediatek,mt8183-mdp3-ccorr21 22  reg:23    maxItems: 124 25  mediatek,gce-client-reg:26    $ref: /schemas/types.yaml#/definitions/phandle-array27    items:28      items:29        - description: phandle of GCE30        - description: GCE subsys id31        - description: register offset32        - description: register size33    description: The register of client driver can be configured by gce with34      4 arguments defined in this property. Each GCE subsys id is mapping to35      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.36 37  mediatek,gce-events:38    description:39      The event id which is mapping to the specific hardware event signal40      to gce. The event id is defined in the gce header41      include/dt-bindings/gce/<chip>-gce.h of each chips.42    $ref: /schemas/types.yaml#/definitions/uint32-array43 44  clocks:45    minItems: 146 47required:48  - compatible49  - reg50  - mediatek,gce-client-reg51  - mediatek,gce-events52  - clocks53 54additionalProperties: false55 56examples:57  - |58    #include <dt-bindings/clock/mt8183-clk.h>59    #include <dt-bindings/gce/mt8183-gce.h>60 61    mdp3_ccorr: mdp3-ccorr@1401c000 {62      compatible = "mediatek,mt8183-mdp3-ccorr";63      reg = <0x1401c000 0x1000>;64      mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;65      mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,66                            <CMDQ_EVENT_MDP_CCORR_EOF>;67      clocks = <&mmsys CLK_MM_MDP_CCORR>;68    };69