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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Smart Voltage Scaling (SVS)8 9maintainers:10  - Roger Lu <roger.lu@mediatek.com>11  - Matthias Brugger <matthias.bgg@gmail.com>12  - Kevin Hilman <khilman@kernel.org>13 14description: |+15  The SVS engine is a piece of hardware which has several16  controllers(banks) for calculating suitable voltage to17  different power domains(CPU/GPU/CCI) according to18  chip process corner, temperatures and other factors. Then DVFS19  driver could apply SVS bank voltage to PMIC/Buck.20 21properties:22  compatible:23    enum:24      - mediatek,mt8183-svs25      - mediatek,mt8186-svs26      - mediatek,mt8188-svs27      - mediatek,mt8192-svs28      - mediatek,mt8195-svs29 30  reg:31    maxItems: 132    description: Address range of the MTK SVS controller.33 34  interrupts:35    maxItems: 136 37  clocks:38    maxItems: 139    description: Main clock for MTK SVS controller to work.40 41  clock-names:42    const: main43 44  nvmem-cells:45    minItems: 146    description:47      Phandle to the calibration data provided by a nvmem device.48    items:49      - description: SVS efuse for SVS controller50      - description: Thermal efuse for SVS controller51 52  nvmem-cell-names:53    items:54      - const: svs-calibration-data55      - const: t-calibration-data56 57  resets:58    maxItems: 159 60  reset-names:61    items:62      - const: svs_rst63 64required:65  - compatible66  - reg67  - interrupts68  - clocks69  - clock-names70  - nvmem-cells71  - nvmem-cell-names72 73additionalProperties: false74 75examples:76  - |77    #include <dt-bindings/clock/mt8183-clk.h>78    #include <dt-bindings/interrupt-controller/arm-gic.h>79    #include <dt-bindings/interrupt-controller/irq.h>80 81    soc {82        #address-cells = <2>;83        #size-cells = <2>;84 85        svs@1100b000 {86            compatible = "mediatek,mt8183-svs";87            reg = <0 0x1100b000 0 0x1000>;88            interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;89            clocks = <&infracfg CLK_INFRA_THERM>;90            clock-names = "main";91            nvmem-cells = <&svs_calibration>, <&thermal_calibration>;92            nvmem-cell-names = "svs-calibration-data", "t-calibration-data";93        };94    };95