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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: GENI Serial Engine QUP Wrapper Controller8 9maintainers:10 - Bjorn Andersson <bjorn.andersson@linaro.org>11 12description: |13 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper14 is a programmable module for supporting a wide range of serial interfaces15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial16 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP17 Wrapper controller is modeled as a node with zero or more child nodes each18 representing a serial engine.19 20properties:21 compatible:22 enum:23 - qcom,geni-se-qup24 - qcom,geni-se-i2c-master-hub25 26 reg:27 description: QUP wrapper common register address and length.28 maxItems: 129 30 clock-names:31 minItems: 132 maxItems: 233 34 clocks:35 minItems: 136 maxItems: 237 38 "#address-cells":39 const: 240 41 "#size-cells":42 const: 243 44 ranges: true45 46 interconnects:47 maxItems: 148 49 interconnect-names:50 const: qup-core51 52 iommus:53 maxItems: 154 55 dma-coherent: true56 57required:58 - compatible59 - reg60 - clock-names61 - clocks62 - "#address-cells"63 - "#size-cells"64 - ranges65 66patternProperties:67 "spi@[0-9a-f]+$":68 type: object69 description: GENI serial engine based SPI controller. SPI in master mode70 supports up to 50MHz, up to four chip selects, programmable71 data path from 4 bits to 32 bits and numerous protocol72 variants.73 $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#74 75 "i2c@[0-9a-f]+$":76 type: object77 description: GENI serial engine based I2C controller.78 $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#79 80 "serial@[0-9a-f]+$":81 type: object82 description: GENI Serial Engine based UART Controller.83 $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#84 85allOf:86 - if:87 properties:88 compatible:89 contains:90 const: qcom,geni-se-i2c-master-hub91 then:92 properties:93 clock-names:94 items:95 - const: s-ahb96 97 clocks:98 items:99 - description: Slave AHB Clock100 101 iommus: false102 103 patternProperties:104 "spi@[0-9a-f]+$": false105 "serial@[0-9a-f]+$": false106 else:107 properties:108 clock-names:109 items:110 - const: m-ahb111 - const: s-ahb112 113 clocks:114 items:115 - description: Master AHB Clock116 - description: Slave AHB Clock117 118additionalProperties: false119 120examples:121 - |122 #include <dt-bindings/clock/qcom,gcc-sdm845.h>123 #include <dt-bindings/interrupt-controller/arm-gic.h>124 125 soc {126 #address-cells = <2>;127 #size-cells = <2>;128 129 geniqup@8c0000 {130 compatible = "qcom,geni-se-qup";131 reg = <0 0x008c0000 0 0x6000>;132 clock-names = "m-ahb", "s-ahb";133 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,134 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;135 #address-cells = <2>;136 #size-cells = <2>;137 ranges;138 139 i2c0: i2c@a94000 {140 compatible = "qcom,geni-i2c";141 reg = <0 0xa94000 0 0x4000>;142 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;143 clock-names = "se";144 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;145 pinctrl-names = "default", "sleep";146 pinctrl-0 = <&qup_1_i2c_5_active>;147 pinctrl-1 = <&qup_1_i2c_5_sleep>;148 #address-cells = <1>;149 #size-cells = <0>;150 };151 152 uart0: serial@a88000 {153 compatible = "qcom,geni-uart";154 reg = <0 0xa88000 0 0x7000>;155 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;156 clock-names = "se";157 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;158 pinctrl-names = "default", "sleep";159 pinctrl-0 = <&qup_1_uart_3_active>;160 pinctrl-1 = <&qup_1_uart_3_sleep>;161 };162 };163 };164 165...166