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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: |+8 TI Programmable Real-Time Unit and Industrial Communication Subsystem9 10maintainers:11 - Suman Anna <s-anna@ti.com>12 13description: |+14 15 The Programmable Real-Time Unit and Industrial Communication Subsystem16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and19 instruction RAMs, some internal peripheral modules to facilitate industrial20 communication, and an interrupt controller.21 22 The programmable nature of the PRUs provide flexibility to implement custom23 peripheral interfaces, fast real-time responses, or specialized data handling.24 The common peripheral modules include the following,25 - an Ethernet MII_RT module with two MII ports26 - an MDIO port to control external Ethernet PHYs27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial28 Ethernet functions29 - an Enhanced Capture Module (eCAP)30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events31 - a 16550-compatible UART to support PROFIBUS32 - Enhanced GPIO with async capture and serial support33 34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address36 0x0, but also has access to a secondary Data RAM (primary to the other PRU37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are39 common to both the PRU cores. Each PRU core also has a private instruction40 RAM, and specific register spaces for Control and Debug functionalities.41 42 Various sub-modules within a PRU-ICSS subsystem are represented as individual43 nodes and are defined using a parent-child hierarchy depending on their44 integration within the IP and the SoC. These nodes are described in the45 following sections.46 47 48 PRU-ICSS Node49 ==============50 Each PRU-ICSS instance is represented as its own node with the individual PRU51 processor cores, the memories node, an INTC node and an MDIO node represented52 as child nodes within this PRUSS node. This node shall be a child of the53 corresponding interconnect bus nodes or target-module nodes.54 55 See ../../mfd/syscon.yaml for generic SysCon binding details.56 57 58properties:59 $nodename:60 pattern: "^(pruss|icssg)@[0-9a-f]+$"61 62 compatible:63 enum:64 - ti,am3356-pruss # for AM335x SoC family65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 066 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 167 - ti,am5728-pruss # for AM57xx SoC family68 - ti,am625-pruss # for K3 AM62x SoC family69 - ti,am642-icssg # for K3 AM64x SoC family70 - ti,am654-icssg # for K3 AM65x SoC family71 - ti,j721e-icssg # for K3 J721E SoC family72 - ti,k2g-pruss # for 66AK2G SoC family73 74 reg:75 maxItems: 176 77 "#address-cells":78 const: 179 80 "#size-cells":81 const: 182 83 ranges:84 maxItems: 185 86 dma-ranges:87 maxItems: 188 89 dma-coherent: true90 91 power-domains:92 description: |93 This property is as per sci-pm-domain.txt.94 95patternProperties:96 97 memories@[a-f0-9]+$:98 description: |99 The various Data RAMs within a single PRU-ICSS unit are represented as a100 single node with the name 'memories'.101 102 type: object103 104 properties:105 reg:106 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.107 items:108 - description: Address and size of the Data RAM0.109 - description: Address and size of the Data RAM1.110 - description: |111 Address and size of the Shared Data RAM. Note that on AM437x one112 of two PRUSS units don't contain Shared RAM, while the second one113 has it.114 115 reg-names:116 minItems: 2117 items:118 - const: dram0119 - const: dram1120 - const: shrdram2121 122 required:123 - reg124 - reg-names125 126 additionalProperties: false127 128 cfg@[a-f0-9]+$:129 description: |130 PRU-ICSS configuration space. CFG sub-module represented as a SysCon.131 132 type: object133 additionalProperties: false134 135 properties:136 compatible:137 items:138 - const: ti,pruss-cfg139 - const: syscon140 141 "#address-cells":142 const: 1143 144 "#size-cells":145 const: 1146 147 reg:148 maxItems: 1149 150 ranges:151 maxItems: 1152 153 clocks:154 type: object155 156 properties:157 "#address-cells":158 const: 1159 160 "#size-cells":161 const: 0162 163 patternProperties:164 coreclk-mux@[a-f0-9]+$:165 description: |166 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules167 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or168 ICSSG_ICLK. This node models this clock mux and should have the169 name "coreclk-mux".170 171 type: object172 173 properties:174 '#clock-cells':175 const: 0176 177 clocks:178 items:179 - description: ICSSG_CORE Clock180 - description: ICSSG_ICLK Clock181 182 assigned-clocks:183 maxItems: 1184 185 assigned-clock-parents:186 maxItems: 1187 description: |188 Standard assigned-clocks-parents definition used for selecting189 mux parent (one of the mux input).190 191 reg:192 maxItems: 1193 194 required:195 - clocks196 197 additionalProperties: false198 199 iepclk-mux@[a-f0-9]+$:200 description: |201 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or202 CORE_CLK (OCP_CLK in older SoCs). This node models this clock203 mux and should have the name "iepclk-mux".204 205 type: object206 207 properties:208 '#clock-cells':209 const: 0210 211 clocks:212 items:213 - description: ICSSG_IEP Clock214 - description: Core Clock (OCP Clock in older SoCs)215 216 assigned-clocks:217 maxItems: 1218 219 assigned-clock-parents:220 maxItems: 1221 description: |222 Standard assigned-clocks-parents definition used for selecting223 mux parent (one of the mux input).224 225 reg:226 maxItems: 1227 228 required:229 - clocks230 231 additionalProperties: false232 233 additionalProperties: false234 235 iep@[a-f0-9]+$:236 description: |237 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet238 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,239 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs).240 IEP is used for creating PTP clocks and generating PPS signals.241 242 type: object243 244 mii-rt@[a-f0-9]+$:245 description: |246 Real-Time Ethernet to support multiple industrial communication protocols.247 MII-RT sub-module represented as a SysCon.248 249 type: object250 251 properties:252 compatible:253 items:254 - const: ti,pruss-mii255 - const: syscon256 257 reg:258 maxItems: 1259 260 additionalProperties: false261 262 mii-g-rt@[a-f0-9]+$:263 description: |264 The Real-time Media Independent Interface to support multiple industrial265 communication protocols (G stands for Gigabit). MII-G-RT sub-module266 represented as a SysCon.267 268 type: object269 270 properties:271 compatible:272 items:273 - const: ti,pruss-mii-g274 - const: syscon275 276 reg:277 maxItems: 1278 279 additionalProperties: false280 281 ^pa-stats@[a-f0-9]+$:282 description: |283 PA-STATS sub-module represented as a SysCon. PA_STATS is a set of284 registers where different statistics related to ICSSG, are dumped by285 ICSSG firmware. This syscon sub-module will help the device to286 access/read/write those statistics.287 288 type: object289 290 additionalProperties: false291 292 properties:293 compatible:294 items:295 - const: ti,pruss-pa-st296 - const: syscon297 298 reg:299 maxItems: 1300 301 interrupt-controller@[a-f0-9]+$:302 description: |303 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance304 that is common to all the PRU cores. This should be represented as an305 interrupt-controller node.306 $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#307 type: object308 309 mdio@[a-f0-9]+$:310 description: |311 MDIO Node. Each PRUSS has an MDIO module that can be used to control312 external PHYs. The MDIO module used within the PRU-ICSS is an instance of313 the MDIO Controller used in TI Davinci SoCs.314 $ref: /schemas/net/ti,davinci-mdio.yaml#315 type: object316 317 "^(pru|rtu|txpru)@[0-9a-f]+$":318 description: |319 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc320 device through a PRU child node each. Each node can optionally be rendered321 inactive by using the standard DT string property, "status". The ICSSG IP322 present on K3 SoCs have additional auxiliary PRU cores with slightly323 different IP integration.324 $ref: /schemas/remoteproc/ti,pru-rproc.yaml#325 type: object326 327required:328 - compatible329 - reg330 - ranges331 332additionalProperties: false333 334# Due to inability of correctly verifying sub-nodes with an @address through335# the "required" list, the required sub-nodes below are commented out for now.336 337# required:338# - memories339# - interrupt-controller340# - pru341 342allOf:343 - if:344 properties:345 compatible:346 contains:347 enum:348 - ti,k2g-pruss349 - ti,am654-icssg350 - ti,j721e-icssg351 - ti,am642-icssg352 then:353 required:354 - power-domains355 356 - if:357 properties:358 compatible:359 contains:360 enum:361 - ti,k2g-pruss362 then:363 required:364 - dma-coherent365 366examples:367 - |368 369 /* Example 1 AM33xx PRU-ICSS */370 pruss: pruss@0 {371 compatible = "ti,am3356-pruss";372 reg = <0x0 0x80000>;373 #address-cells = <1>;374 #size-cells = <1>;375 ranges;376 377 pruss_mem: memories@0 {378 reg = <0x0 0x2000>,379 <0x2000 0x2000>,380 <0x10000 0x3000>;381 reg-names = "dram0", "dram1", "shrdram2";382 };383 384 pruss_cfg: cfg@26000 {385 compatible = "ti,pruss-cfg", "syscon";386 #address-cells = <1>;387 #size-cells = <1>;388 reg = <0x26000 0x2000>;389 ranges = <0x00 0x26000 0x2000>;390 391 clocks {392 #address-cells = <1>;393 #size-cells = <0>;394 395 pruss_iepclk_mux: iepclk-mux@30 {396 reg = <0x30>;397 #clock-cells = <0>;398 clocks = <&l3_gclk>, /* icss_iep */399 <&pruss_ocp_gclk>; /* icss_ocp */400 };401 };402 };403 404 pruss_mii_rt: mii-rt@32000 {405 compatible = "ti,pruss-mii", "syscon";406 reg = <0x32000 0x58>;407 };408 409 pruss_intc: interrupt-controller@20000 {410 compatible = "ti,pruss-intc";411 reg = <0x20000 0x2000>;412 interrupt-controller;413 #interrupt-cells = <3>;414 interrupts = <20 21 22 23 24 25 26 27>;415 interrupt-names = "host_intr0", "host_intr1",416 "host_intr2", "host_intr3",417 "host_intr4", "host_intr5",418 "host_intr6", "host_intr7";419 };420 421 pru0: pru@34000 {422 compatible = "ti,am3356-pru";423 reg = <0x34000 0x2000>,424 <0x22000 0x400>,425 <0x22400 0x100>;426 reg-names = "iram", "control", "debug";427 firmware-name = "am335x-pru0-fw";428 };429 430 pru1: pru@38000 {431 compatible = "ti,am3356-pru";432 reg = <0x38000 0x2000>,433 <0x24000 0x400>,434 <0x24400 0x100>;435 reg-names = "iram", "control", "debug";436 firmware-name = "am335x-pru1-fw";437 };438 439 pruss_mdio: mdio@32400 {440 compatible = "ti,davinci_mdio";441 reg = <0x32400 0x90>;442 clocks = <&dpll_core_m4_ck>;443 clock-names = "fck";444 bus_freq = <1000000>;445 #address-cells = <1>;446 #size-cells = <0>;447 };448 };449 450 - |451 452 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */453 #include <dt-bindings/interrupt-controller/arm-gic.h>454 pruss1: pruss@0 {455 compatible = "ti,am4376-pruss1";456 reg = <0x0 0x40000>;457 #address-cells = <1>;458 #size-cells = <1>;459 ranges;460 461 pruss1_mem: memories@0 {462 reg = <0x0 0x2000>,463 <0x2000 0x2000>,464 <0x10000 0x8000>;465 reg-names = "dram0", "dram1", "shrdram2";466 };467 468 pruss1_cfg: cfg@26000 {469 compatible = "ti,pruss-cfg", "syscon";470 #address-cells = <1>;471 #size-cells = <1>;472 reg = <0x26000 0x2000>;473 ranges = <0x00 0x26000 0x2000>;474 475 clocks {476 #address-cells = <1>;477 #size-cells = <0>;478 479 pruss1_iepclk_mux: iepclk-mux@30 {480 reg = <0x30>;481 #clock-cells = <0>;482 clocks = <&sysclk_div>, /* icss_iep */483 <&pruss_ocp_gclk>; /* icss_ocp */484 };485 };486 };487 488 pruss1_mii_rt: mii-rt@32000 {489 compatible = "ti,pruss-mii", "syscon";490 reg = <0x32000 0x58>;491 };492 493 pruss1_intc: interrupt-controller@20000 {494 compatible = "ti,pruss-intc";495 reg = <0x20000 0x2000>;496 interrupt-controller;497 #interrupt-cells = <3>;498 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,499 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,500 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,501 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,502 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,503 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,504 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;505 interrupt-names = "host_intr0", "host_intr1",506 "host_intr2", "host_intr3",507 "host_intr4",508 "host_intr6", "host_intr7";509 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */510 };511 512 pru1_0: pru@34000 {513 compatible = "ti,am4376-pru";514 reg = <0x34000 0x3000>,515 <0x22000 0x400>,516 <0x22400 0x100>;517 reg-names = "iram", "control", "debug";518 firmware-name = "am437x-pru1_0-fw";519 };520 521 pru1_1: pru@38000 {522 compatible = "ti,am4376-pru";523 reg = <0x38000 0x3000>,524 <0x24000 0x400>,525 <0x24400 0x100>;526 reg-names = "iram", "control", "debug";527 firmware-name = "am437x-pru1_1-fw";528 };529 530 pruss1_mdio: mdio@32400 {531 compatible = "ti,davinci_mdio";532 reg = <0x32400 0x90>;533 clocks = <&dpll_core_m4_ck>;534 clock-names = "fck";535 bus_freq = <1000000>;536 #address-cells = <1>;537 #size-cells = <0>;538 };539 };540 541...542