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1LogicoreIP designed compatible with Xilinx ZYNQ family.2-------------------------------------------------------3 4General concept5---------------6 7LogicoreIP design to provide the isolation between processing system8and programmable logic. Also provides the list of register set to configure9the frequency.10 11Required properties:12- compatible: shall be one of:13 "xlnx,vcu"14 "xlnx,vcu-logicoreip-1.0"15- reg : The base offset and size of the VCU_PL_SLCR register space.16- clocks: phandle for aclk and pll_ref clocksource17- clock-names: The identification string, "aclk", is always required for18 the axi clock. "pll_ref" is required for pll.19Example:20 21 xlnx_vcu: vcu@a0040000 {22 compatible = "xlnx,vcu-logicoreip-1.0";23 reg = <0x0 0xa0040000 0x0 0x1000>;24 clocks = <&si570_1>, <&clkc 71>;25 clock-names = "pll_ref", "aclk";26 };27