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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Amlogic Audio AXG TDM formatters8 9maintainers:10  - Jerome Brunet <jbrunet@baylibre.com>11 12properties:13  compatible:14    enum:15      - amlogic,g12a-tdmout16      - amlogic,sm1-tdmout17      - amlogic,axg-tdmout18      - amlogic,g12a-tdmin19      - amlogic,sm1-tdmin20      - amlogic,axg-tdmin21 22  clocks:23    items:24      - description: Peripheral clock25      - description: Bit clock26      - description: Bit clock input multiplexer27      - description: Sample clock28      - description: Sample clock input multiplexer29 30  clock-names:31    items:32      - const: pclk33      - const: sclk34      - const: sclk_sel35      - const: lrclk36      - const: lrclk_sel37 38  reg:39    maxItems: 140 41  resets:42    maxItems: 143 44required:45  - compatible46  - reg47  - clocks48  - clock-names49 50allOf:51  - $ref: component-common.yaml#52 53  - if:54      properties:55        compatible:56          contains:57            enum:58              - amlogic,g12a-tdmin59              - amlogic,sm1-tdmin60              - amlogic,g12a-tdmout61              - amlogic,sm1-tdmout62    then:63      required:64        - resets65 66    else:67      properties:68        resets: false69 70unevaluatedProperties: false71 72examples:73  - |74    #include <dt-bindings/clock/axg-audio-clkc.h>75    #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>76 77    audio-controller@500 {78        compatible = "amlogic,g12a-tdmout";79        reg = <0x500 0x40>;80        resets = <&clkc_audio AUD_RESET_TDMOUT_A>;81        clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,82                 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,83                 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,84                 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,85                 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;86        clock-names = "pclk", "sclk", "sclk_sel",87                      "lrclk", "lrclk_sel";88    };89