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1BROADCOM Cygnus Audio I2S/TDM/SPDIF controller2 3Required properties:4 - compatible : "brcm,cygnus-audio"5 - #address-cells: 32bit valued, 1 cell.6 - #size-cells: 32bit valued, 0 cell.7 - reg : Should contain audio registers location and length8 - reg-names: names of the registers listed in "reg" property9 Valid names are "aud" and "i2s_in". "aud" contains a10 set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains11 a set of I2S_IN registers.12 - clocks: PLL and leaf clocks used by audio ports13 - assigned-clocks: PLL and leaf clocks14 - assigned-clock-parents: parent clocks of the assigned clocks15 (usually the PLL)16 - assigned-clock-rates: List of clock frequencies of the17 assigned clocks18 - clock-names: names of 3 leaf clocks used by audio ports19 Valid names are "ch0_audio", "ch1_audio", "ch2_audio"20 - interrupts: audio DMA interrupt number21 22SSP Subnode properties:23- reg: The index of ssp port interface to use24 Valid value are 0, 1, 2, or 3 (for spdif)25 26Example:27 cygnus_audio: audio@180ae000 {28 compatible = "brcm,cygnus-audio";29 #address-cells = <1>;30 #size-cells = <0>;31 reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;32 reg-names = "aud", "i2s_in";33 clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,34 <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,35 <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,37 <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,38 <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,39 <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;41 assigned-clock-rates = <1769470191>,42 <0>,43 <0>,44 <0>;45 clock-names = "ch0_audio", "ch1_audio", "ch2_audio";46 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;47 48 ssp0: ssp_port@0 {49 reg = <0>;50 };51 52 ssp1: ssp_port@1 {53 reg = <1>;54 };55 56 ssp2: ssp_port@2 {57 reg = <2>;58 };59 60 spdif: spdif_port@3 {61 reg = <3>;62 };63 };64