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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/cirrus,cs4271.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cirrus Logic CS4271 audio CODEC8 9maintainers:10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>11 - Nikita Shubin <nikita.shubin@maquefel.me>12 13description:14 The CS4271 is a stereo audio codec. This device supports both the I2C15 and the SPI bus.16 17allOf:18 - $ref: dai-common.yaml#19 - $ref: /schemas/spi/spi-peripheral-props.yaml#20 21properties:22 compatible:23 const: cirrus,cs427124 25 reg:26 maxItems: 127 28 spi-cpha: true29 30 spi-cpol: true31 32 '#sound-dai-cells':33 const: 034 35 reset-gpios:36 description:37 This pin will be deasserted before communication to the codec starts.38 maxItems: 139 40 va-supply:41 description: Analog power supply.42 43 vd-supply:44 description: Digital power supply.45 46 vl-supply:47 description: Serial Control Port power supply.48 49 port:50 $ref: audio-graph-port.yaml#51 unevaluatedProperties: false52 53 cirrus,amuteb-eq-bmutec:54 description:55 When given, the Codec's AMUTEB=BMUTEC flag is enabled.56 type: boolean57 58 cirrus,enable-soft-reset:59 description: |60 The CS4271 requires its LRCLK and MCLK to be stable before its RESET61 line is de-asserted. That also means that clocks cannot be changed62 without putting the chip back into hardware reset, which also requires63 a complete re-initialization of all registers.64 65 One (undocumented) workaround is to assert and de-assert the PDN bit66 in the MODE2 register. This workaround can be enabled with this DT67 property.68 69 Note that this is not needed in case the clocks are stable70 throughout the entire runtime of the codec.71 type: boolean72 73required:74 - compatible75 - reg76 77unevaluatedProperties: false78 79examples:80 - |81 #include <dt-bindings/gpio/gpio.h>82 spi {83 #address-cells = <1>;84 #size-cells = <0>;85 codec@0 {86 compatible = "cirrus,cs4271";87 reg = <0>;88 #sound-dai-cells = <0>;89 spi-max-frequency = <6000000>;90 spi-cpol;91 spi-cpha;92 reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;93 port {94 endpoint {95 remote-endpoint = <&i2s_ep>;96 };97 };98 };99 };100 101...102