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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller8 9description:10 The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of11 a signal associated with an input clock into a signal associated with a12 different output clock. The driver currently works as a Front End of DPCM13 with other Back Ends Audio controller such as ESAI, SSI and SAI. It has14 three pairs to support three substreams within totally 10 channels.15 16maintainers:17 - Shawn Guo <shawnguo@kernel.org>18 - Sascha Hauer <s.hauer@pengutronix.de>19 20properties:21 compatible:22 oneOf:23 - enum:24 - fsl,imx35-asrc25 - fsl,imx53-asrc26 - fsl,imx8qm-asrc27 - fsl,imx8qxp-asrc28 - items:29 - enum:30 - fsl,imx6sx-asrc31 - fsl,imx6ul-asrc32 - const: fsl,imx53-asrc33 34 reg:35 maxItems: 136 37 interrupts:38 maxItems: 139 40 dmas:41 maxItems: 642 43 dma-names:44 items:45 - const: rxa46 - const: rxb47 - const: rxc48 - const: txa49 - const: txb50 - const: txc51 52 clocks:53 maxItems: 1954 55 clock-names:56 items:57 - const: mem58 - const: ipg59 - const: asrck_060 - const: asrck_161 - const: asrck_262 - const: asrck_363 - const: asrck_464 - const: asrck_565 - const: asrck_666 - const: asrck_767 - const: asrck_868 - const: asrck_969 - const: asrck_a70 - const: asrck_b71 - const: asrck_c72 - const: asrck_d73 - const: asrck_e74 - const: asrck_f75 - const: spba76 77 power-domains:78 maxItems: 179 80 fsl,asrc-rate:81 $ref: /schemas/types.yaml#/definitions/uint3282 description: The mutual sample rate used by DPCM Back Ends83 84 fsl,asrc-width:85 $ref: /schemas/types.yaml#/definitions/uint3286 description: The mutual sample width used by DPCM Back Ends87 enum: [16, 24]88 89 fsl,asrc-clk-map:90 $ref: /schemas/types.yaml#/definitions/uint3291 description:92 Defines clock map used in driver93 <0> - select the map for asrc0 in imx8qm/imx8qxp94 <1> - select the map for asrc1 in imx8qm/imx8qxp95 enum: [0, 1]96 97 big-endian:98 type: boolean99 description:100 If this property is absent, the little endian mode will be in use as101 default. Otherwise, the big endian mode will be in use for all the102 device registers.103 104 fsl,asrc-format:105 $ref: /schemas/types.yaml#/definitions/uint32106 description:107 Defines a mutual sample format used by DPCM Back Ends, which can108 replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE).109 enum: [2, 6]110 111required:112 - compatible113 - reg114 - interrupts115 - dmas116 - dma-names117 - clocks118 - clock-names119 - fsl,asrc-rate120 - fsl,asrc-width121 122allOf:123 - if:124 properties:125 compatible:126 contains:127 enum:128 - fsl,imx8qm-asrc129 - fsl,imx8qxp-asrc130 then:131 required:132 - fsl,asrc-clk-map133 else:134 properties:135 fsl,asrc-clk-map: false136 137 - if:138 properties:139 compatible:140 contains:141 enum:142 - fsl,imx8qm-asrc143 - fsl,imx8qxp-asrc144 then:145 required:146 - power-domains147 148additionalProperties: false149 150examples:151 - |152 #include <dt-bindings/interrupt-controller/irq.h>153 #include <dt-bindings/clock/imx6qdl-clock.h>154 asrc: asrc@2034000 {155 compatible = "fsl,imx53-asrc";156 reg = <0x02034000 0x4000>;157 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;158 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,159 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,160 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,161 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,162 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,163 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,164 <&clks IMX6QDL_CLK_SPBA>;165 clock-names = "mem", "ipg", "asrck_0",166 "asrck_1", "asrck_2", "asrck_3", "asrck_4",167 "asrck_5", "asrck_6", "asrck_7", "asrck_8",168 "asrck_9", "asrck_a", "asrck_b", "asrck_c",169 "asrck_d", "asrck_e", "asrck_f", "spba";170 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,171 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;172 dma-names = "rxa", "rxb", "rxc",173 "txa", "txb", "txc";174 fsl,asrc-rate = <48000>;175 fsl,asrc-width = <16>;176 };177