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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller8 9maintainers:10 - Shengjiu Wang <shengjiu.wang@nxp.com>11 12description: |13 The Freescale S/PDIF audio block is a stereo transceiver that allows the14 processor to receive and transmit digital audio via an coaxial cable or15 a fibre cable.16 17properties:18 compatible:19 enum:20 - fsl,imx35-spdif21 - fsl,vf610-spdif22 - fsl,imx6sx-spdif23 - fsl,imx8qm-spdif24 - fsl,imx8qxp-spdif25 - fsl,imx8mq-spdif26 - fsl,imx8mm-spdif27 - fsl,imx8mn-spdif28 - fsl,imx8ulp-spdif29 30 reg:31 maxItems: 132 33 interrupts:34 minItems: 135 items:36 - description: Combined or receive interrupt37 - description: Transmit interrupt38 39 dmas:40 items:41 - description: DMA controller phandle and request line for RX42 - description: DMA controller phandle and request line for TX43 44 dma-names:45 items:46 - const: rx47 - const: tx48 49 clocks:50 items:51 - description: The core clock of spdif controller.52 - description: Clock for tx0 and rx0.53 - description: Clock for tx1 and rx1.54 - description: Clock for tx2 and rx2.55 - description: Clock for tx3 and rx3.56 - description: Clock for tx4 and rx4.57 - description: Clock for tx5 and rx5.58 - description: Clock for tx6 and rx6.59 - description: Clock for tx7 and rx7.60 - description: The spba clock is required when SPDIF is placed as a bus61 slave of the Shared Peripheral Bus and when two or more bus masters62 (CPU, DMA or DSP) try to access it. This property is optional depending63 on the SoC design.64 - description: PLL clock source for 8kHz series rate, optional.65 - description: PLL clock source for 11khz series rate, optional.66 minItems: 967 68 clock-names:69 items:70 - const: core71 - const: rxtx072 - const: rxtx173 - const: rxtx274 - const: rxtx375 - const: rxtx476 - const: rxtx577 - const: rxtx678 - const: rxtx779 - const: spba80 - const: pll8k81 - const: pll11k82 minItems: 983 84 big-endian:85 $ref: /schemas/types.yaml#/definitions/flag86 description: |87 If this property is absent, the native endian mode will be in use88 as default, or the big endian mode will be in use for all the device89 registers. Set this flag for HCDs with big endian descriptors and big90 endian registers.91 92 power-domains:93 maxItems: 194 95required:96 - compatible97 - reg98 - interrupts99 - dmas100 - dma-names101 - clocks102 - clock-names103 104additionalProperties: false105 106allOf:107 - if:108 properties:109 compatible:110 enum:111 - fsl,imx8qm-spdif112 - fsl,imx8qxp-spdif113 then:114 properties:115 interrupts:116 minItems: 2117 else:118 properties:119 interrupts:120 maxItems: 1121 122 - if:123 properties:124 compatible:125 contains:126 enum:127 - fsl,imx8qm-spdif128 - fsl,imx8qxp-spdif129 then:130 required:131 - power-domains132 133examples:134 - |135 spdif@2004000 {136 compatible = "fsl,imx35-spdif";137 reg = <0x02004000 0x4000>;138 interrupts = <0 52 0x04>;139 dmas = <&sdma 14 18 0>,140 <&sdma 15 18 0>;141 dma-names = "rx", "tx";142 clocks = <&clks 197>, <&clks 3>,143 <&clks 197>, <&clks 107>,144 <&clks 0>, <&clks 118>,145 <&clks 62>, <&clks 139>,146 <&clks 0>;147 clock-names = "core", "rxtx0",148 "rxtx1", "rxtx2",149 "rxtx3", "rxtx4",150 "rxtx5", "rxtx6",151 "rxtx7";152 big-endian;153 };154