brintos

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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek AFE PCM controller for MT79868 9maintainers:10  - Maso Huang <maso.huang@mediatek.com>11 12properties:13  compatible:14    oneOf:15      - const: mediatek,mt7986-afe16      - items:17          - enum:18              - mediatek,mt7981-afe19              - mediatek,mt7988-afe20          - const: mediatek,mt7986-afe21 22  reg:23    maxItems: 124 25  interrupts:26    maxItems: 127 28  clocks:29    minItems: 530    items:31      - description: audio bus clock32      - description: audio 26M clock33      - description: audio intbus clock34      - description: audio hopping clock35      - description: audio pll clock36      - description: mux for pcm_mck37      - description: audio i2s/pcm mck38 39  clock-names:40    minItems: 541    items:42      - const: bus_ck43      - const: 26m_ck44      - const: l_ck45      - const: aud_ck46      - const: eg2_ck47      - const: sel48      - const: i2s_m49 50required:51  - compatible52  - reg53  - interrupts54  - clocks55  - clock-names56 57allOf:58  - if:59      properties:60        compatible:61          contains:62            const: mediatek,mt7986-afe63    then:64      properties:65        clocks:66          items:67            - description: audio bus clock68            - description: audio 26M clock69            - description: audio intbus clock70            - description: audio hopping clock71            - description: audio pll clock72        clock-names:73          items:74            - const: bus_ck75            - const: 26m_ck76            - const: l_ck77            - const: aud_ck78            - const: eg2_ck79 80  - if:81      properties:82        compatible:83          contains:84            const: mediatek,mt7981-afe85    then:86      properties:87        clocks:88          items:89            - description: audio bus clock90            - description: audio 26M clock91            - description: audio intbus clock92            - description: audio hopping clock93            - description: audio pll clock94            - description: mux for pcm_mck95        clock-names:96          items:97            - const: bus_ck98            - const: 26m_ck99            - const: l_ck100            - const: aud_ck101            - const: eg2_ck102            - const: sel103 104  - if:105      properties:106        compatible:107          contains:108            const: mediatek,mt7988-afe109    then:110      properties:111        clocks:112          items:113            - description: audio bus clock114            - description: audio 26M clock115            - description: audio intbus clock116            - description: audio hopping clock117            - description: audio pll clock118            - description: mux for pcm_mck119            - description: audio i2s/pcm mck120        clock-names:121          items:122            - const: bus_ck123            - const: 26m_ck124            - const: l_ck125            - const: aud_ck126            - const: eg2_ck127            - const: sel128            - const: i2s_m129 130additionalProperties: false131 132examples:133  - |134    #include <dt-bindings/interrupt-controller/arm-gic.h>135    #include <dt-bindings/interrupt-controller/irq.h>136    #include <dt-bindings/clock/mt7986-clk.h>137 138    afe@11210000 {139        compatible = "mediatek,mt7986-afe";140        reg = <0x11210000 0x9000>;141        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;142        clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,143                 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,144                 <&infracfg_ao CLK_INFRA_AUD_L_CK>,145                 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,146                 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;147        clock-names = "bus_ck",148                      "26m_ck",149                      "l_ck",150                      "aud_ck",151                      "eg2_ck";152        assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,153                          <&topckgen CLK_TOP_AUD_L_SEL>,154                          <&topckgen CLK_TOP_A_TUNER_SEL>;155        assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,156                                 <&apmixedsys CLK_APMIXED_APLL2>,157                                 <&topckgen CLK_TOP_APLL2_D4>;158    };159 160...161